This is a video regarding the overview of hardware accelerator (HWA) 2.0 introduced in TAWR294x TI mmWave devices. The agenda for this video includes key features of HWA 2.0, functions of sub-blocks in the accelerator engine, APIs used for programming and an example use-case of it tying together all the sub-blocks. Initially, the video introduces the hardware accelerator and how it can be used to offload repetitive operations from DSP/main processor.

This video show-cases key features of HWA2.0 in the pre-processing block, FFT engine, compression engine, post-processing block and finally some miscellaneous capabilities of it which include context switching and lock-step for FSMs (Finite State Machines). Then the sub-blocks in the accelerator engine along with their functions are explained. The sub-blocks include state-machine, parameter-set configuration memory, input formatter, output formatter and core-computational unit.

Lastly, the video has a dedicated section which explains various paths in the core-computational engine which include FFT path, CFAR path, compression path and local maxima path. Followed by this, we explain some general APIs available in mmWave_MCUPlus_SDK for programming the HWA 2.0. Then, there is the section of video which explains use-case of HWA2.0 along with DSP/main processor for classification task. Finally, the video ends with comparison of key enhancements done in HWA2.0 from HWA1.0.