SBAS774B Data sheet

SBAS774B May 2016 – December 2021 ADC32RF80 , ADC32RF83

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RMP|72
- MPQF396A
RRH|72
- MPQF526

Thermal pad, mechanical data (Package|Pins)

Orderable Information

8.3.3.1 Using SYSREF

The ADC32RF8x uses SYSREF information to reset the clock divider, the NCO phase, and the LMFC counter of the JESD interface. The device provides flexibility to provide SYSREF information either from dedicated pins or through SPI register bits. As shown in Figure 8-11, SYSREF is asserted by a low-to-high transition on the SYSREF pins or a 0-to-1 change in the ASSERT SYSREF REG bit when using SPI registers.

Figure 8-11 Using SYSREF to Reset the Clock Divider, the NCO, and the LMFC Counter

The ADC32RF8x samples the SYSREF signal on the input clock rising edge. Required setup and hold time are listed in the Section 6.10 table. The input clock divider gets reset each time that SYSREF is asserted, whereas the NCO phase and the LMFC counter of the JESD interface are reset on each SYSREF assertion after disregarding the first two assertions, as shown in Table 8-1.

Table 8-1 Asserting SYSREF

SYSREF ASSERTION INDEX	ACTION
SYSREF ASSERTION INDEX	INPUT CLOCK DIVIDER	NCO PHASE	LMFC COUNTER
1	Gets reset	Does not get reset	Does not get reset
2	Gets reset	Does not get reset	Does not get reset
3	Gets reset	Gets reset	Gets reset
4 and onwards	Gets reset	Gets reset	Gets reset

The SYSREF use-cases can be classified broadly into two categories:

SYSREF is applied as aperiodic multi-shot pulses.
Figure 8-12 shows a case when only a counted number of pulses are applied as SYSREF to the ADC.

Alternatively, the SYSREF buffer can be powered down with the PDN SYSREF bit.
Figure 8-12 SYSREF Used as Aperiodic, Finite Number of Pulses
After the first SYSREF pulse is applied, allow the DLL in the clock path to settle by waiting for the t_DLL time (> 40 µs) before applying the second pulse. During this time, mask the SYSREF going to the input clock divider by setting the MASK CLKDIV SYSREF bit so that the divider output phase remains stable. The NCO phase and LMFC counter are reset on the third SYSREF pulse. After the third SYSREF pulse, the SYSREF going to the NCO and JESD block can be disabled by setting the MASK NCO SYSREF bit to avoid any unwanted resets.
SYSREF is applied as a periodic pulse.
Figure 8-13 shows how SYSREF can be applied as a continuous periodic waveform.

t_SYSREF is a period of the SYSREF waveform.

Alternatively, the SYSREF buffer can be powered down using the PDN SYSREF bit.
Figure 8-13 SYSREF Used as a Periodic Waveform
After applying the SYSREF signal, DLL must be allowed to lock, and the NCO phase and LMFC counter must be allowed to reset by waiting for at least the t_DLL (40 µs) + 2 × t_SYSREF time. Then, the SYSREF going to the NCO and JESD can be masked by setting the MASK NCO SYSREF register bit.