SBAS778B June 2017 – August 2019 ADS1287
PRODUCTION DATA.
The ADC is reset in one of three ways: at power-up, by the RESET pin, or by the RESET command. By pin, drive RESET low for at least 2 fCLK cycles to force a reset. The ADC is held in reset until the pin is released high. By command, reset takes effect on the next rising fCLK edge occurring after the eighth rising edge of SCLK. In order to ensure a functional reset by command, the SPI interface may itself require reset; see the Serial Interface section for details. When the ADC is reset, registers are reset to default values and the conversions are synchronized on the next rising edge of CLK. Reset timing is illustrated in Figure 5, the Timing Requirements table, and the Switching Characteristics table.