SBOS588B December   2011  – June 2019 AFE030

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Block Diagram
  4. 4 Revision History
  5. 5 Description, continued
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics: Transmitter (Tx), Tx_DAC
    5. 7.5  Electrical Characteristics: Transmitter (Tx), Tx_PGA
    6. 7.6  Electrical Characteristics: Transmitter (Tx), Tx_FILTER
    7. 7.7  Electrical Characteristics: Power Amplifier (PA)
    8. 7.8  Electrical Characteristics: Receiver (Rx), Rx PGA1
    9. 7.9  Electrical Characteristics: Receiver (Rx), Rx Filter
    10. 7.10 Electrical Characteristics: Receiver (Rx), Rx PGA2
    11. 7.11 Electrical Characteristics: Digital
    12. 7.12 Electrical Characteristics: Two-Wire Interface
    13. 7.13 Electrical Characteristics: Zero-Crossing Detector
    14. 7.14 Electrical Characteristics: Internal Bias Generator
    15. 7.15 Electrical Characteristics: Power Supply
    16. 7.16 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Requirements
    2. 8.2 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 PA Block
      2. 9.3.2 Tx Block
      3. 9.3.3 Rx Block
      4. 9.3.4 DAC Block
      5. 9.3.5 REF1 and REF2 Blocks
      6. 9.3.6 Zero Crossing Detector Block
      7. 9.3.7 ETx and ERx Blocks
    4. 9.4 Power Supplies
    5. 9.5 Pin Descriptions
      1. 9.5.1 Current Overload
      2. 9.5.2 Thermal Overload
    6. 9.6 Calibration Modes
      1. 9.6.1 Tx Calibration Mode
      2. 9.6.2 Rx Calibration Mode
    7. 9.7 Serial Interface
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
    3. 10.3 Line-Coupling Circuit
    4. 10.4 Circuit Protection
    5. 10.5 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI™ (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
        3. 11.1.1.3 WEBENCH Filter Designer
      2. 11.1.2 Powerline Communications Developer’s Kit
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.7 Serial Interface

The AFE030 is controlled through a serial interface that allows read/write access to the control and data registers. A host SPI frame consists of a R/W bit, a 6-bit register address, and eight data bits. Data are shifted out on the falling edge of SCLK and latched on the rising edge of SCLK. Refer to the Timing Diagrams for a valid host SPI communications protocol. Table 10 through Table 19 show the complete register information.

Table 10. Data Register

REGISTER ADDRESS DEFAULT FUNCTION
ENABLE1 01h 00h Block enable or disable
GAIN SELECT 02h 32h Rx and Tx gain select
ENABLE2 03h 00h Block enable or disable
CONTROL1 04h 00h Frequency select and calibration, Tx and Rx status
CONTROL2 05h 01h Interrupt enable
RESET 09h 00h Interrupt status and device reset
DIE_ID 0Ah 01h Die name
REVISION 0Bh 02h Die revision

Table 11. Command Register

BIT NAME LOCATION
(15 = MSB)		 R/W FUNCTION
ADDR8 8 W Register address bit
ADDR9 9 W Register address bit
ADDR10 10 W Register address bit
ADDR11 11 W Register address bit
ADDR12 12 W Register address bit
ADDR13 13 W Register address bit
ADDR14 14 W Register address bit
R/W 15 W Read/write: read = 1, write = 0

Table 12. Enable1 Register: Address 00h
Default: 00h

Enable1 Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
PA 0 0 R/W This bit is used to enable/disable the PA block.
0 = Disabled
1 = Enabled
TX 1 0 R/W This bit is used to enable/disable the Tx block.
0 = Disabled
1 = Enabled
RX 2 0 R/W This bit is used to enable/disable the Rx block.
0 = Disabled
1 = Enabled
ERX 3 0 R/W This bit is used to enable/disable the ERx block.
0 = Disabled
1 = Enabled
ETX 4 0 R/W This bit is used to enable/disable the ETx block.
0 = Disabled
1 = Enabled
DAC 5 0 R/W This bit is used to enable/disable the DAC block.
0 = DAC disabled; switch is connected to Tx_PGA_IN pin.
1 = DAC enabled; switch is connected to DAC output.
— 6 0 — Reserved
— 7 0 — Reserved

Table 13. Gain Select Register: Address 02h
Default: 32h

Gain Select Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
RX1G-0,
RX1G-1		 0, 1 0, 1 R/W This bit is used to set the gain of the Rx PGA1.
00 = 0.25 V/V
01 = 0.5 V/V
10 = 1 V/V
11 = 2 V/V
RX2G-0,
RX2G-1		 2, 3 0, 0 R/W This bit is used to set the gain of the Rx PGA2.
00 = 1 V/V
01 = 4 V/V
10 = 16 V/V
11 = 64 V/V
TXG-0,
TXG-1		 4, 5 1, 1 R/W This bit is used to set the gain of the Tx PGA.
00 = 0.25 V/V
01 = 0.5 V/V
10 = 0.707 V/V
11 = 1 V/V
— 6 0 — Reserved
— 7 0 — Reserved

Table 14. Enable2 Register: Address 03h
Default: 00h

Enable2 Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
ZC 0 0 R/W This bit is used to enable/disable the ZC block.
0 = Disabled
1 = Enabled
REF1 1 0 R/W This bit is used to enable/disable the REF1 block.
0 = Disabled
1 = Enabled
REF2 2 0 R/W This bit is used to enable/disable the REF2 block.
0 = Disabled
1 = Enabled
PA_OUT 3 0 R/W This bit is used to enable/disable the PA output stage.
When the PA output stage is enabled it functions normally with a low output impedance, capable of driving heavy loads.
When the PA output stage is disabled it is placed into a high impedance state.
0 = Disabled
1 = Enabled
— 4 0 — Reserved
— 5 0 — Reserved
— 6 0 — Reserved
— 7 0 — Reserved

Table 15. Control1 Register: Address 04h
Default: 00h

Control1 Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
TX_CAL 0 0 R/W This bit is used to enable/disable the TX calibration mode.
0 = Disabled
1 = Enabled
RX_CAL 1 0 R/W This bit is used to enable/disable the RX calibration mode.
0 = Disabled
1 = Enabled
— 2 0 — Reserved
CA_CBCD 3 0 R/W This bit is used to select the frequency response of the Tx filter and Rx filter.
0 = CENELEC A
1 = CENELEC B, C, D
— 4 0 — Reserved
— 5 0 — Reserved
TX_FLAG 6 0 R This bit is used to indicate the status of the Tx block.
0 = Tx block is not ready for transmission
1 = Tx block is ready for transmission
RX_FLAG 7 0 R This bit is used to indicate the status of the Rx block.
0 = Rx block is not ready for reception
1 = Rx block is ready for reception

Table 16. Control2 Register: Address 05h
Default: 01h

Control2 Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
— 0 0 — Reserved
— 1 0 — Reserved
— 2 0 — Reserved
— 3 0 — Reserved
— 4 0 — Reserved
T_FLAG_EN 5 0 R/W This bit is used to enable/disable the T_flag bit in the RESET Register.
0 = Disabled
1 = Enabled
I_FLAG_EN 6 0 R/W This bit is used to enable/disable the I_flag bit in the RESET Register.
0 = Disabled
1 = Enabled
— 7 X — Reserved

Table 17. RESET Register: Address 09h
Default: 00h

Reset Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
-- 0 0 -- Reserved
-- 1 0 -- Reserved
SOFTRST0,
SOFTRST1,
SOFTRST2		 2, 3, 4 0, 0, 0 W These bits are used to perform a software reset of the ENABLE1, ENABLE2, CONTROL2, CONTROL3, and GAIN SELECT registers. Writing '101' to these registers performs a software reset.
T_FLAG 5 0 R/W This bit is used to indicate the status of a PA thermal overload.
0 = On read, indicates that no thermal overload has occurred since the last reset.
0 = On write, resets this bit.
1 = On read, indicates that a thermal overload has occurred since the last reset. Remains latched until reset.
I_FLAG 6 0 R/W This bit is used to indicate the status of a PA output current overload.
0 = On read indicates that no current overload has occurred since the last reset.
0 = On write, resets this bit.
1 = On read indicates that a current overload has occurred since the last reset. Remains latched until reset.
— 7 0 — Reserved

Table 18. DieID Register: Address 0Ah
Default: 01h

DieID Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
DIE ID<0> 0 1 R The DieID Register is hard-wired.
DIE ID<1> 1 0 R The DieID Register is hard-wired.
DIE ID<2> 2 0 R The DieID Register is hard-wired.
DIE ID<3> 3 0 R The DieID Register is hard-wired.
DIE ID<4> 4 0 R The DieID Register is hard-wired.
DIE ID<5> 5 0 R The DieID Register is hard-wired.
DIE ID<6> 6 0 R The DieID Register is hard-wired.
DIE ID<7> 7 0 R The DieID Register is hard-wired.

Table 19. Revision Register: Address 0Bh
Default: 02h

Revision Register <7:0>
BIT NAME LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
REVISION ID<0> 0 0 R The Revision Register is hard-wired.
REVISION ID<1> 1 1 R The Revision Register is hard-wired.
REVISION ID<2> 2 0 R The Revision Register is hard-wired.
REVISION ID<3> 3 0 R The Revision Register is hard-wired.
REVISION ID<4> 4 0 R The Revision Register is hard-wired.
REVISION ID<5> 5 0 R The Revision Register is hard-wired.
REVISION ID<6> 6 0 R The Revision Register is hard-wired.
REVISION ID<7> 7 0 R The Revision Register is hard-wired.