SBOS948F February   2019  – May 2021 BUF634A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: Wide-Bandwidth Mode
    6. 7.6 Electrical Characteristics: Low-Quiescent Current Mode
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Current
      2. 8.3.2 Thermal Shutdown
      3. 8.3.3 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Adjustable Bandwidth
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 High-Frequency Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Dissipation and Thermal Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 SOIC Layout Guidelines (D Package Without a Thermal Pad)
      2. 11.1.2 HSOIC Layout Guidelines (DDA Package With a Thermal Pad)
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 TINA-TI (Free Software Download)
        2. 12.1.2.2 TI Precision Designs
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DDA|8
  • DRB|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1.2 HSOIC Layout Guidelines (DDA Package With a Thermal Pad)

Figure 11-1 shows the DDA package top-side etch and via pattern.

GUID-B7C6A212-0926-46BF-829C-CD714A2503C2-low.gifFigure 11-1 DDA Thermal Pad Integrated Circuit Package PCB Etch and Via Pattern
  1. Use an etch for the leads and the thermal pad.
  2. Place 13 vias in the thermal pad area. These vias must be 0.01 inch (0.254 mm) in diameter. Keep the vias small so that solder wicking through the vias is not a problem during reflow.
  3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area, and help dissipate the heat generated by the BUF634A. These additional vias may be larger than the 0.01-inch (0.254 mm) diameter vias directly under the thermal pad because they are not in the area that requires soldering. As a result, wicking is not a problem.
  4. The thermal pad is internally connected with V–. Therefore, always short the thermal pad to the same potential as V– externally as well.
  5. Connect all vias used under the thermal pad to remove heat to the V– plane.
  6. When connecting these vias to the V– plane, do not use the typical web or spoke connection methodology. Web and spoke connections have a high thermal resistance that slows the heat transfer during soldering. The vias under the BUF634A thermal pad must connect to the internal thermal plane or thermal pour with a complete connection around the entire circumference of the plated-through hole.
  7. The top-side solder mask must leave the pins of the package and the thermal pad area with the 13 vias exposed.
  8. Apply solder paste to the exposed thermal pad area and all of the device pins.
  9. With these preparatory steps in place, the device is placed in position and run through the solder reflow operation as any standard surface-mount component.