SLAS564G August   2007  – October 2016 CDCE937 , CDCEL937

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: CLK_IN
    7. 6.7 Timing Requirements: SDA/SCL
    8. 6.8 EEPROM Specification
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Setting
      2. 8.3.2 Default Device Setting
      3. 8.3.3 SDA/SCL Serial Interface
      4. 8.3.4 Data Protocol
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA/SCL Hardware Interface
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 SDA/SCL Configuration Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The CDCE937 and CDCEL937 devices are modular PLL-based, low-cost, high-performance, programmable clock synthesizers, multipliers, and dividers. They generate up to seven output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using one of the three integrated configurable PLLs. The CDCx937 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL937 and 2.5 V to 3.3 V for CDCE937.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF.

Additionally, a selectable on-chip VCXO allows synchronization of the output frequency to an external control signal, that is, the PWM signal.

The deep M/N divider ratio allows the generation of 0 ppm audio/video, networking (WLAN, BlueTooth, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency such as 27 MHz.

All PLLs supports SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking which is a common technique to reduce electro-magnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.

The device supports non-volatile EEPROM programming for ease-customized application. It is preset to a factory default configuration (see Default Device Setting). It can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through SDA/SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for output-disable function.

The CDCx937 operates in a 1.8-V environment. It is characterized for operation from –40°C to 85°C.

8.2 Functional Block Diagram

CDCE937 CDCEL937 fbd_las564.gif

8.3 Feature Description

8.3.1 Control Terminal Setting

The CDCEx937 has three user-definable control terminals (S0, S1, and S2) which allow external control of device settings. They can be programmed to any of the following setting:

  • Spread spectrum clocking selection → spread type and spread amount selection
  • Frequency selection → switching between any of two user-defined frequencies
  • Output state selection → output configuration and power down control

The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.

Table 1. Control Terminal Definition

EXTERNAL
CONTROL BITS		 PLL1 SETTING PLL2 SETTING PLL3 SETTING Y1 SETTING
Control Function PLL
Frequency
Selection		 SSC Selection Output Y2/Y3
Selection 		PLL
Frequency
Selection		 SSC Selection Output Y4/Y5
Selection 		PLL
Frequency
Selection		 SSC
Selection		 Output Y6/Y7
Selection 		Output Y1
and Power-Down
Selection

Table 2. PLLx Setting (Can Be Selected for Each PLL Individual)

SSC SELECTION (CENTER/DOWN)(1)
SSCx [3-bits] CENTER DOWN
0 0 0 0% (off) 0% (off)
0 0 1 ±0.25% –0.25%
0 1 0 ±0.5% –0.5%
0 1 1 ±0.75% –0.75%
1 0 0 ±1% –1%
1 0 1 ±1.25% –1.25%
1 1 0 ±1.5% –1.5%
1 1 1 ±2% –2%
FREQUENCY SELECTION(2)
FSx FUNCTION
0 Frequency0
1 Frequency1
OUTPUT SELECTION(3) (Y2 ... Y7)
YxYx FUNCTION
0 State0
1 State1
(1) Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register
(2) Frequency0 and Frequency1 can be any frequency within the specified fVCO range
(3) State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down, 3-state, low or active

Table 3. Y1 Setting(1)

Y1 SELECTION
Y1 FUNCTION
0 State 0
1 State 1
(1) State0 and State1 are user definable in Generic Configuration Register and can be power down, 3-state, low, or active.

S1/SDA and S2/SCL pins of the CDCEx937 are dual function pins. In default configuration they are defined as SDA/SCL for the serial interface. They can be programmed as control-pins (S1/S2) by setting the relevant bits in the EEPROM. Note that the changes to the Control register (Bit [6] of Byte [02]) have no effect until they are written into the EEPROM.

Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is forced to GND, the two control-pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).

S0 is not a multi-use pin, it is a control pin only.

8.3.2 Default Device Setting

The internal EEPROM of CDCEx937 is preconfigured as shown in Figure 6. (The input frequency is passed through to the output as a default.) This allows the device to operate in default mode without the extra production step of program it. The default setting appears after power is supplied or after power-down or power-up sequence until it is reprogrammed by the user to a different application configuration. A new register setting is programmed through the serial SDA/SCL Interface.

CDCE937 CDCEL937 default_cir_las564.gif Figure 6. Default Device Setting

Table 4 shows the factory default setting for the Control Terminal Register (external control pins). In normal operation, all 8 register settings are available, but in the default configuration only the first two settings (0 and 1) can be selected with S0, as S1 and S2 configured as programming pins in default mode.

Table 4. Factory Default Setting for Control Terminal Register(1)

Y1 PLL1 SETTINGS PLL2 SETTINGS PLL3 SETTINGS
EXTERNAL
CONTROL PINS		 OUTPUT
SELECTION		 FREQUENCY
SELECTION		 SSC
SELECTION		 OUTPUT
SELECTION		 FREQUENCY
SELECTION		 SSC
SELECTION		 OUTPUT
SELECTION		 FREQUENCY
SELECTION		 SSC
SELECTION		 OUTPUT
SELECTION
S2 S1 S0 Y1 FS1 SSC1 Y2Y3 FS2 SSC2 Y4Y5 FS3 SSC3 Y6Y7
SCL (I2C) SDA (I2C) 0 3-state fVCO1_0 off 3-state fVCO2_0 off 3-state fVCO1_0 off 3-state
SCL (I2C) SDA (I2C) 1 enabled fVCO1_0 off enabled fVCO2_0 off enabled fVCO1_0 off enabled
(1) In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA/SCL. They do not have any control-pin function but they are internally interpreted as if S1=0 and S2=0. However, S0 is a control-pin which in the default mode switches all outputs ON or OFF (as previously predefined).

8.3.3 SDA/SCL Serial Interface

The CDCEx937 operates as a slave device of the 2-wire serial SDA/SCL bus, compatible with the popular SMBus or I2C specification. It operates in the standard-mode transfer (up to 100 kbit/s) and fast-mode transfer (up to 400kbit/s) and supports 7-bit addressing.

The S1/SDA and S2/SCL pins of the CDC9xx are dual function pins. In the default configuration they are used as SDA/SCL serial programming interface. They can be reprogrammed as general purpose control pins, S1 and S2, by changing the corresponding EEPROM setting, Byte 02, Bit [6].

CDCE937 CDCEL937 tim_dia_cas847.gif Figure 7. Timing Diagram for SDA/SCL Serial Control Interface

8.3.4 Data Protocol

The device supports Byte Write and Byte Read and Block Write and Block Read operations.

For Byte Write/Read operations, the system controller can individually access addressed bytes.

For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with most significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of Bytes read-out are defined by Byte Count in the Generic Configuration Register. At Block Read instruction all bytes defined in the Byte Count has to be readout to correctly finish the read cycle.

Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to each transferred byte independent of whether this is a Byte Write or a Block Write sequence.

If the EEPROM Write Cycle is initiated, the internal SDA register contents are written into the EEPROM. During this write cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can be read during the programming sequence (Byte Read or Block Read). The programming status can be monitored by reading EEPIP, Byte 01–Bit [6].

The offset of the indexed byte is encoded in the command code, as described in Table 5.

Table 5. Slave Receiver Address (7 Bits)

DEVICE A6 A5 A4 A3 A2 A1(1) A0(1) R/W
CDCEx913 1 1 0 0 1 0 1 1/0
CDCEx925 1 1 0 0 1 0 0 1/0
CDCEx937 1 1 0 1 1 0 1 1/0
CDCEx949 1 1 0 1 1 0 0 1/0
(1) Address bits A0 and A1 are programmable through the SDA/SCL bus (Byte 01, Bit [1:0]). This allows addressing up to 4 devices connected to the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation.

8.4 Device Functional Modes

8.4.1 SDA/SCL Hardware Interface

Figure 8 shows how the CDCEx937 clock synthesizer is connected to the SDA/SCL serial interface bus. Multiple devices can be connected to the bus but the speed may require reduction (400 kHz is the maximum) if many devices are connected.

Note that the pullup resistors (RP) depends on the supply voltage, bus capacitance, and number of connected devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at
VOLmax = 0.4 V for the output stages (for more details, see SMBus or I2C Bus specification).

CDCE937 CDCEL937 hardware_las564.gif Figure 8. SDA/SCL Hardware Interface

8.5 Programming

Table 6. Command Code Definition

BIT DESCRIPTION
7 0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
(6:0) Byte Offset for Byte Read, Block Read, Byte Write and Block Write operation.
CDCE937 CDCEL937 prog_seq_cas847.gif Figure 9. Generic Programming Sequence
CDCE937 CDCEL937 byte_wr_cas847.gif Figure 10. Byte Write Protocol
CDCE937 CDCEL937 byte_rd_cas847.gif Figure 11. Byte Read Protocol
CDCE937 CDCEL937 block_wr_cas847.gif
Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose and must not be overwritten.
Figure 12. Block Write Protocol
CDCE937 CDCEL937 block_rd_cas847.gif Figure 13. Block Read Protocol

8.6 Register Maps

8.6.1 SDA/SCL Configuration Registers

The clock input, control pins, PLLs, and output stages are user configurable. The following tables and explanations describe the programmable functions of the CDCEx937. All settings can be manually written into the device through the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software. TI Pro-Clock™ software allows the user to quickly make all settings and automatically calculates the values for optimized performance at lowest jitter.

Table 7. SDA and SCL Registers

ADDRESS OFFSET REGISTER DESCRIPTION TABLE
00h Generic Configuration Register Table 9
10h PLL1 Configuration Register Table 10
20h PLL2 Configuration Register Table 11
30h PLL3 Configuration Register Table 12

The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the Control Terminal Register. The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2 (see Control Terminal Setting).

Table 8. Configuration Register, External Control Terminals

Y1 PLL1 SETTINGS PLL2 SETTINGS PLL3 SETTINGS
EXTERNAL
CONTROL PINS		 OUTPUT
SELECTION		 FREQ.
SELECTION		 SSC
SELECTION		 OUTPUT
SELECTION		 FREQ.
SELECTION		 SSC
SELECTION		 OUTPUT
SELECTION		 FREQ.
SELECTION		 SSC
SELECTION		 OUTPUT
SELECTION
S2 S1 S0 Y1 FS1 SSC1 Y2Y3 FS2 SSC2 Y4Y5 FS3 SSC3 Y6Y7
0 0 0 0 Y1_0 FS1_0 SSC1_0 Y2Y3_0 FS2_0 SSC2_0 Y4Y5_0 FS3_0 SSC3_0 Y6Y7_0
1 0 0 1 Y1_1 FS1_1 SSC1_1 Y2Y3_1 FS2_1 SSC2_1 Y4Y5_1 FS3_1 SSC3_1 Y6Y7_1
2 0 1 0 Y1_2 FS1_2 SSC1_2 Y2Y3_2 FS2_2 SSC2_2 Y4Y5_2 FS3_2 SSC3_2 Y6Y7_2
3 0 1 1 Y1_3 FS1_3 SSC1_3 Y2Y3_3 FS2_3 SSC2_3 Y4Y5_3 FS3_3 SSC3_3 Y6Y7_3
4 1 0 0 Y1_4 FS1_4 SSC1_4 Y2Y3_4 FS2_4 SSC2_4 Y4Y5_4 FS3_4 SSC3_4 Y6Y7_4
5 1 0 1 Y1_5 FS1_5 SSC1_5 Y2Y3_5 FS2_5 SSC2_5 Y4Y5_5 FS3_5 SSC3_5 Y6Y7_5
6 1 1 0 Y1_6 FS1_6 SSC1_6 Y2Y3_6 FS2_6 SSC2_6 Y4Y5_6 FS3_6 SSC3_6 Y6Y7_6
7 1 1 1 Y1_7 FS1_7 SSC1_7 Y2Y3_7 FS2_7 SSC2_7 Y4Y5_7 FS3_7 SSC3_7 Y6Y7_7
Address Offset(1) 04h 13h 10h–12h 15h 23h 20h–22h 25h 33h 30h–32h 35h
(1) Address Offset refers to the byte address in the Configuration Register in the following pages.

Table 9. Generic Configuration Register

OFFSET(1) BIT(2) ACRONYM DEFAULT(3) DESCRIPTION
00h 7 E_EL Xb Device identification (read-only): 1 is CDCE937 (3.3 V), 0 is CDCEL937 (1.8 V)
6:4 RID Xb Revision Identification Number (read only)
3:0 VID 1h Vendor Identification Number (read only)
01h 7 – 0b Reserved – always write 0
6 EEPIP 0b EEPROM Programming Status:(4) (read only) 0 – EEPROM programming is completed
1 – EEPROM is in programming mode
5 EELOCK 0b Permanently Lock EEPROM Data(5) 0 – EEPROM is not locked
1 – EEPROM is permanently locked
4 PWDN 0b Device Power Down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
0 – device active (PLL1 and all outputs are enabled)
1 – device power down (PLL1 in power down and all outputs in 3-state)
3:2 INCLK 00b Input clock selection: 00 – Xtal  01 – VCXO   10 – LVCMOS  11 – reserved
1:0 SLAVE_ADR 01b Programmable Address Bits A0 and A1 of the Slave Receiver Address
02h 7 M1 1b Clock source selection for output Y1: 0 – input clock  1 – PLL1 clock
6 SPICON 0b Operation mode selection for pin 18/19(6)
0 – serial programming interface SDA (pin 19) and SCL (pin 18)
1 – control pins S1 (pin 19) and S2 (pin 18)
5:4 Y1_ST1 11b Y1-State0/1 Definition
3:2 Y1_ST0 01b 00 – device power down (all PLLs in power down and all outputs in 3-State)
01 – Y1 disabled to 3-state		 10 – Y1 disabled to low
11 – Y1 enabled
1:0 Pdiv1 [9:8] 001h 10-Bit Y1-Output-Divider Pdiv1: 0 – divider reset and stand-by
1-to-1023 – divider value
03h 7:0 Pdiv1 [7:0]
04h 7 Y1_7 0b Y1_ST0/Y1_ST1 State Selection(7)
6 Y1_6 0b 0 – State0 (predefined by Y1_ST0)
1 – State1 (predefined by Y1_ST1)
5 Y1_5 0b
4 Y1_4 0b
3 Y1_3 0b
2 Y1_2 0b
1 Y1_1 1b
0 Y1_0 0b
05h 7:3 XCSEL 0Ah Crystal Load Capacitor Selection(8) 00h → 0 pF
01h → 1 pF
02h → 2 pF
  :
14h-to-1Fh → 20 pF
2:0 0b Reserved – do not write other than 0
06h 7:1 BCOUNT 40h 7-Bit Byte Count (defines the number of bytes which is sent from this device at the next Block Read transfer); all bytes have to be read out to correctly finish the read cycle.)
0 EEWRITE 0b Initiate EEPROM Write Cycle(4) (9) 0– no EEPROM write cycle
1 – start EEPROM write cycle (internal configuration register is saved to the EEPROM)
07h-0Fh — 0h Unused address range
(1) Writing data beyond ‘40h’ may affect device function.
(2) All data transferred with the MSB first.
(3) Unless customer-specific setting.
(4) During EEPROM programming, no data is allowed to be sent to the device through the SDA/SCL bus until the programming sequence is completed. However, data can be read out during the programming sequence (Byte Read or Block Read).
(5) If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. There is no further programming possible. However, data can still be written through the SDA/SCL bus to the internal register to change device function on the fly. But new data can no longer be saved to the EEPROM. EELOCK is effective only, if written into the EEPROM!
(6) Selection of control pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.
(7) These are the bits of the Control Terminal Register. The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2.
(8) The internal load capacitor (C1, C2) has to be used to achieve the best clock performance. External capacitors must be used only to finely adjust CL by a few pF's. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20 pF. For CL > 20 pF, use additional external capacitors. Also, the value of the device input capacitance has to be considered which always adds 1.5 pF (6 pF//2 pF) to the selected CL. For more information about VCXO configuration and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).
(9) Note: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level high does not trigger an EEPROM WRITE cycle. The EEWRITE bit has to be reset to low after the programming is completed. The programming status can be monitored by reading out EEPIP. If EELOCK is set to high, no EEPROM programming is possible.

Table 10. PLL1 Configuration Register

OFFSET(1) BIT(2) ACRONYM DEFAULT(3) DESCRIPTION
10h 7:5 SSC1_7 [2:0] 000b SSC1: PLL1 SSC Selection (Modulation Amount)(4)
4:2 SSC1_6 [2:0] 000b Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		 Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0 SSC1_5 [2:1] 000b
11h 7 SSC1_5 [0]
6:4 SSC1_4 [2:0] 000b
3:1 SSC1_3 [2:0] 000b
0 SSC1_2 [2] 000b
12h 7:6 SSC1_2 [1:0]
5:3 SSC1_1 [2:0] 000b
2:0 SSC1_0 [2:0] 000b
13h 7 FS1_7 0b FS1_x: PLL1 Frequency Selection(4)
6 FS1_6 0b 0 – fVCO1_0 (predefined by PLL1_0 – Multiplier/Divider value)
1 – fVCO1_1 (predefined by PLL1_1 – Multiplier/Divider value)
5 FS1_5 0b
4 FS1_4 0b
3 FS1_3 0b
2 FS1_2 0b
1 FS1_1 0b
0 FS1_0 0b
14h 7 MUX1 1b PLL1 Multiplexer: 0 – PLL1
1 – PLL1 Bypass (PLL1 is in power down)
6 M2 1b Output Y2 Multiplexer: 0 – Pdiv1
1 – Pdiv2
5:4 M3 10b Output Y3 Multiplexer: 00 – Pdiv1-Divider
01 – Pdiv2-Divider
10 – Pdiv3-Divider
11 – reserved
3:2 Y2Y3_ST1 11b Y2, Y3-State0/1definition: 00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State
10–Y2/Y3 disabled to low
11 – Y2/Y3 enabled
1:0 Y2Y3_ST0 01b
15h 7 Y2Y3_7 0b Y2Y3_x Output State Selection(4)
6 Y2Y3_6 0b 0 – state0 (predefined by Y2Y3_ST0)
1 – state1 (predefined by Y2Y3_ST1)
5 Y2Y3_5 0b
4 Y2Y3_4 0b
3 Y2Y3_3 0b
2 Y2Y3_2 0b
1 Y2Y3_1 1b
0 Y2Y3_0 0b
16h 7 SSC1DC 0b PLL1 SSC down/center selection: 0 – down    1 – center
6:0 Pdiv2 01h 7-Bit Y2-Output-Divider Pdiv2: 0 – reset and stand-by   1-to-127 is divider value
17h 7 — 0b Reserved – do not write others than 0
6:0 Pdiv3 01h 7-Bit Y3-Output-Divider Pdiv3: 0 – reset and stand-by    1-to-127 is divider value
18h 7:0 PLL1_0N [11:4] 004h PLL1_0(5): 30-Bit Multiplier/Divider value for frequency fVCO1_0
(for more information, see PLL Frequency Planning).
19h 7:4 PLL1_0N [3:0]
3:0 PLL1_0R [8:5] 000h
1Ah 7:3 PLL1_0R[4:0]
2:0 PLL1_0Q [5:3] 10h
1Bh 7:5 PLL1_0Q [2:0]
4:2 PLL1_0P [2:0] 010b
1:0 VCO1_0_RANGE 00b fVCO1_0 range selection: 00 – fVCO1_0 < 125 MHz
01 – 125 MHz ≤ fVCO1_0 < 150 MHz
10 – 150 MHz ≤ fVCO1_0 < 175 MHz
11 – fVCO1_0 ≥ 175 MHz
1Ch 7:0 PLL1_1N [11:4] 004h PLL1_1(5): 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information see PLL Frequency Planning).
1Dh 7:4 PLL1_1N [3:0]
3:0 PLL1_1R [8:5] 000h
1Eh 7:3 PLL1_1R[4:0]
2:0 PLL1_1Q [5:3] 10h
1Fh 7:5 PLL1_1Q [2:0]
4:2 PLL1_1P [2:0] 010b
1:0 VCO1_1_RANGE 00b fVCO1_1 range selection: 00 – fVCO1_1 < 125 MHz
01 – 125 MHz ≤ fVCO1_1 < 150 MHz
10 – 150 MHz ≤ fVCO1_1 < 175 MHz
11 – fVCO1_1 ≥ 175 MHz
(1) Writing data beyond 40h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2.
(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096

Table 11. PLL2 Configuration Register

OFFSET(1) BIT(2) ACRONYM DEFAULT(3) DESCRIPTION
20h 7:5 SSC2_7 [2:0] 000b SSC2: PLL2 SSC Selection (Modulation Amount)(4)
4:2 SSC2_6 [2:0] 000b Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		 Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0 SSC2_5 [2:1] 000b
21h 7 SSC2_5 [0]
6:4 SSC2_4 [2:0] 000b
3:1 SSC2_3 [2:0] 000b
0 SSC2_2 [2] 000b
22h 7:6 SSC2_2 [1:0]
5:3 SSC2_1 [2:0] 000b
2:0 SSC2_0 [2:0] 000b
23h 7 FS2_7 0b FS2_x: PLL2 Frequency Selection(4)
6 FS2_6 0b 0 – fVCO2_0 (predefined by PLL2_0 – Multiplier/Divider value)
1 – fVCO2_1 (predefined by PLL2_1 – Multiplier/Divider value)
5 FS2_5 0b
4 FS2_4 0b
3 FS2_3 0b
2 FS2_2 0b
1 FS2_1 0b
0 FS2_0 0b
24h 7 MUX2 1b PLL2 Multiplexer: 0 – PLL2
1 – PLL2 Bypass (PLL2 is in power down)
6 M4 1b Output Y4 Multiplexer: 0 – Pdiv2
1 – Pdiv4
5:4 M5 10b Output Y5 Multiplexer: 00 – Pdiv2-Divider
01 – Pdiv4-Divider
10 – Pdiv5-Divider
11 – reserved
3:2 Y4Y5_ST1 11b Y4, Y5-State0/1definition: 00 – Y4/Y5 disabled to 3-State (PLL2 is in power down)
01 – Y4/Y5 disabled to 3-State
10–Y4/Y5 disabled to low
11 – Y4/Y5 enabled
1:0 Y4Y5_ST0 01b
25h 7 Y4Y5_7 0b Y4Y5_x Output State Selection(4)
6 Y4Y5_6 0b 0 – state0 (predefined by Y4Y5_ST0)
1 – state1 (predefined by Y4Y5_ST1)
5 Y4Y5_5 0b
4 Y4Y5_4 0b
3 Y4Y5_3 0b
2 Y4Y5_2 0b
1 Y4Y5_1 1b
0 Y4Y5_0 0b
26h 7 SSC2DC 0b PLL2 SSC down/center selection: 0 – down
1 – center
6:0 Pdiv4 01h 7-Bit Y4-Output-Divider Pdiv4: 0 – reset and stand-by   1-to-127 – divider value
27h 7 — 0b Reserved – do not write others than 0
6:0 Pdiv5 01h 7-Bit Y5-Output-Divider Pdiv5: 0 – reset and stand-by    1-to-127 – divider value
28h 7:0 PLL2_0N [11:4 004h PLL2_0(5): 30-Bit Multiplier/Divider value for frequency fVCO2_0
(for more information see PLL Frequency Planning).
29h 7:4 PLL2_0N [3:0]
3:0 PLL2_0R [8:5] 000h
2Ah 7:3 PLL2_0R[4:0]
2:0 PLL2_0Q [5:3] 10h
2Bh 7:5 PLL2_0Q [2:0]
4:2 PLL2_0P [2:0] 010b
1:0 VCO2_0_RANGE 00b fVCO2_0 range selection: 00 – fVCO2_0 < 125 MHz
01 – 125 MHz ≤ fVCO2_0 < 150 MHz
10 – 150 MHz ≤ fVCO2_0 < 175 MHz
11 – fVCO2_0 ≥ 175 MHz
2Ch 7:0 PLL2_1N [11:4] 004h PLL2_1(5): 30-Bit Multiplier/Divider value for frequency fVCO2_1
(for more information see PLL Frequency Planning).
2Dh 7:4 PLL2_1N [3:0]
3:0 PLL2_1R [8:5] 000h
2Eh 7:3 PLL2_1R[4:0]
2:0 PLL2_1Q [5:3] 10h
2Fh 7:5 PLL2_1Q [2:0]
4:2 PLL2_1P [2:0] 010b
1:0 VCO2_1_RANGE 00b fVCO2_1 range selection: 00 – fVCO2_1 < 125 MHz
01 – 125 MHz ≤ fVCO2_1 < 150 MHz
10 – 150 MHz ≤ fVCO2_1 < 175 MHz
11 – fVCO2_1 ≥ 175 MHz
(1) Writing data beyond 40h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2.
(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096

Table 12. PLL3 Configuration Register

OFFSET(1) BIT(2) ACRONYM DEFAULT(3) DESCRIPTION
30h 7:5 SSC3_7 [2:0] 000b SSC3: PLL3 SSC Selection (Modulation Amount)(4)
4:2 SSC3_6 [2:0] 000b Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		 Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0 SSC3_5 [2:1] 000b
31h 7 SSC3_5 [0]
6:4 SSC3_4 [2:0] 000b
3:1 SSC3_3 [2:0] 000b
0 SSC3_2 [2] 000b
32h 7:6 SSC3_2 [1:0]
5:3 SSC3_1 [2:0] 000b
2:0 SSC3_0 [2:0] 000b
33h 7 FS3_7 0b FS3_x: PLL3 Frequency Selection(4)
6 FS3_6 0b 0 – fVCO3_0 (predefined by PLL3_0 – Multiplier/Divider value)
1 – fVCO3_1 (predefined by PLL3_1 – Multiplier/Divider value)
5 FS3_5 0b
4 FS3_4 0b
3 FS3_3 0b
2 FS3_2 0b
1 FS3_1 0b
0 FS3_0 0b
34h 7 MUX3 1b PLL3 Multiplexer: 0 – PLL3
1 – PLL3 Bypass (PLL3 is in power down)
6 M6 1b Output Y6 Multiplexer: 0 – Pdiv4
1 – Pdiv6
5:4 M7 10b Output Y7 Multiplexer: 00 – Pdiv4-Divider
01 – Pdiv6-Divider
10 – Pdiv7-Divider
11 – reserved
3:2 Y6Y7_ST1 11b Y6, Y7-State0/1definition: 00 – Y6/Y7 disabled to 3-State and PLL3 power down
01 – Y6/Y7 disabled to 3-State
10 –Y6/Y7 disabled to low
11 – Y6/Y7 enabled
1:0 Y6Y7_ST0 01b
35h 7 Y6Y7_7 0b Y6Y7_x Output State Selection(4)
6 Y6Y7_6 0b 0 – state0 (predefined by Y6Y7_ST0)
1 – state1 (predefined by Y6Y7_ST1)
5 Y6Y7_5 0b
4 Y6Y7_4 0b
3 Y6Y7_3 0b
2 Y6Y7_2 0b
1 Y6Y7_1 1b
0 Y6Y7_0 0b
36h 7 SSC3DC 0b PLL3 SSC down/center selection: 0 – down  1 – center
6:0 Pdiv6 01h 7-Bit Y6-Output-Divider Pdiv6: 0 – reset and stand-by   1-to-127 – divider value
37h 7 — 0b Reserved – do not write others than 0
6:0 Pdiv7 01h 7-Bit Y7-Output-Divider Pdiv7: 0 – reset and stand-by   1-to-127 – divider value
38h 7:0 PLL3_0N [11:4] 004h PLL3_0(5): 30-Bit Multiplier/Divider value for frequency fVCO3_0
(for more information, see PLL Frequency Planning).
39h 7:4 PLL3_0N [3:0]
3:0 PLL3_0R [8:5] 000h
3Ah 7:3 PLL3_0R[4:0]
2:0 PLL3_0Q [5:3] 10h
3Bh 7:5 PLL3_0Q [2:0]
4:2 PLL3_0P [2:0] 010b
1:0 VCO3_0_RANGE 00b fVCO3_0 range selection: 00 – fVCO3_0 < 125 MHz
01 – 125 MHz ≤ fVCO3_0 < 150 MHz
10 – 150 MHz ≤ fVCO3_0 < 175 MHz
11 – fVCO3_0 ≥ 175 MHz
3Ch 7:0 PLL3_1N [11:4] 004h PLL3_1(5): 30-Bit Multiplier/Divider value for frequency fVCO3_1
(for more information, see PLL Frequency Planning).
3Dh 7:4 PLL3_1N [3:0]
3:0 PLL3_1R [8:5] 000h
3Eh 7:3 PLL3_1R[4:0]
2:0 PLL3_1Q [5:3] 10h
3Fh 7:5 PLL3_1Q [2:0]
4:2 PLL3_1P [2:0] 010b
1:0 VCO3_1_RANGE 00b fVCO3_1 range selection: 00 – fVCO3_1 < 125 MHz
01 – 125 MHz ≤ fVCO3_1 < 150 MHz
10 – 150 MHz ≤ fVCO3_1 < 175 MHz
11 – fVCO3_1 ≥ 175 MHz
(1) Writing data beyond 40h may affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) These are the bits of the Control Terminal Register. The user can pre-define up to eight different control settings. At normal device operation, these setting can be selected by the external control pins, S0, S1, and S2.
(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096