SLAS564G
August 2007 – October 2016
CDCE937
,
CDCEL937
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements: CLK_IN
6.7
Timing Requirements: SDA/SCL
6.8
EEPROM Specification
6.9
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Control Terminal Setting
8.3.2
Default Device Setting
8.3.3
SDA/SCL Serial Interface
8.3.4
Data Protocol
8.4
Device Functional Modes
8.4.1
SDA/SCL Hardware Interface
8.5
Programming
8.6
Register Maps
8.6.1
SDA/SCL Configuration Registers
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Spread Spectrum Clock (SSC)
9.2.2.2
PLL Frequency Planning
9.2.2.3
Crystal Oscillator Start-Up
9.2.2.4
Frequency Adjustment With Crystal Oscillator Pulling
9.2.2.5
Unused Inputs and Outputs
9.2.2.6
Switching Between XO and VCXO Mode
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Third-Party Products Disclaimer
12.1.2
Development Support
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Receiving Notification of Documentation Updates
12.4
Community Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PW|20
MPDS362A
Thermal pad, mechanical data (Package|Pins)
PW|20
QFND419A
Orderable Information
slas564g_oa
slas564g_pm
7 Parameter Measurement Information
Figure 4. Test Load
Figure 5. Test Load for 50-Ω Board Environment