SLAS564G August   2007  – October 2016 CDCE937 , CDCEL937

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: CLK_IN
    7. 6.7 Timing Requirements: SDA/SCL
    8. 6.8 EEPROM Specification
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Setting
      2. 8.3.2 Default Device Setting
      3. 8.3.3 SDA/SCL Serial Interface
      4. 8.3.4 Data Protocol
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA/SCL Hardware Interface
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 SDA/SCL Configuration Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PW Package
20-Pin TSSOP
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
GND 5, 9, 16 G Ground
SCL/S2 18 I SCL: Serial clock input (default configuration), LVCMOS; Internal pullup 500k;
S2: User programmable control input; LVCMOS inputs; Internal pullup 500k
SDA/S1 19 I/O SDA: Bi-directional serial data input/output (default configuration). LVCMOS; Internal pullup 500k;
S1: User programmable control input; LVCMOS inputs; Internal pullup 500k
S0 2 I User programmable control input S0; LVCMOS inputs; Internal pullup 500k
VCtrl 4 I VCXO control voltage, leave open or pullup (approximately 500k) when not used
VDD 3 P 1.8-V power supply for the device
Vddout 6, 10, 13 P CDCEL937: 1.8-V supply for all outputs
CDCE937: 3.3-V or 2.5-V supply for all outputs
Xin/CLK 1 I Crystal oscillator input or LVCMOS clock input (selectable through SDA/SCL bus)
Xout 20 O Crystal oscillator output, leave open or pullup (~500k) when not used
Y1 17 O LVCMOS outputs
Y2 15 O LVCMOS outputs
Y3 14 O LVCMOS outputs
Y4 7 O LVCMOS outputs
Y5 8 O LVCMOS outputs
Y6 12 O LVCMOS outputs
Y7 11 O LVCMOS outputs
(1) G= Ground, I = Input, O = Output, P = Power