The CDCVF25081 has an integrated PLL with a dedicated feedback pin (FBIN) for synchronization and zero-delay. FBIN must be directly routed to a clock output to complete the feedback loop. When no input is applied to the CLKIN pin, the device powers down the outputs by setting them to a low logic level.

Because it is based on a PLL circuitry, the CDCVF25081 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This time is required following power up and application of a fixed-frequency signal at CLKIN and any changes to the PLL reference.

Output duty cycles are adjusted to 50%, independent of duty cycle at CLKIN. Each output has an internal series damping resistor of 25 ohms useful in driving point-to-point loads. Unused outputs can be left floating to reduce overall system cost.

Table 8-1 lists the output bank mapping of the CDCVF25081.