SCAS671B October   2001  – January 2022 CDCVF25081

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
t(lock)PLL lock timef = 100 MHz10µs
t(phoffset)Phase offset (CLKIN to FBIN)f = 8 MHz to 66 MHz,
Vth = VDD/2 (3)		–200200ps
f = 66 MHz to 200 MHz,
Vth = VDD/2 (3)		–150150
tPLHLow-to-high level output propagation delayS2 = High, S1 = Low (PLL bypass),
f = 1 MHz, CL = 25 pF		2.56ns
tPHLHigh-to-low level output propagation delay2.56
tsk(o)Output skew (Yn to Yn) (2)150ps
tsk(pp)Part-to-part skewS2 = high, S1 = high (PLL mode)600ps
S2 = high, S1 = low (PLL bypass)700
tjit(cc)Jitter (cycle-to-cycle)f = 66 MHz to 200 MHz, CL = 15 pF±100ps
f = 66 MHz to 100 MHz, CL = 25 pF,
f = 8 MHz to 66 MHz (see Figure 6-2)		±150
odcOutput duty cyclef = 8 MHz to 200 MHz43%57%
tsk(p)Pulse skewS2 = High, S1 = low (PLL bypass),
f = 1 MHz, CL = 25 pF		0.7ns
tRISERise time rateCL = 15 pF, See Figure 7-40.83.3V/ns
CL = 25 pF, See Figure 7-40.52
tFALLFall time rateCL = 15 pF, See Figure 7-40.83.3V/ns
CL = 25 pF, See Figure 7-40.52
(1) All typical values are at respective nominal VDD.
(2) The tsk(o)specification is only valid for equal loading of all outputs.
(3) Similar waveform at CLKIN and FBIN are required. For phase displacement between CLKIN and Y-outputs see Figure 6-1.