SBAS246B December   2001  – November 2014 DAC8532

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Diagram
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Resistor String
      3. 8.3.3 Output Amplifier
      4. 8.3.4 Serial Interface
      5. 8.3.5 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Shift Register
      2. 8.4.2 SYNC Interrupt
      3. 8.4.3 Power-Down Modes
    5. 8.5 Register Maps
      1. 8.5.1 Operation Examples
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Current Consumption
      2. 9.1.2 Driving Resistive and Capacitive Loads
      3. 9.1.3 Crosstalk and AC Performance
      4. 9.1.4 Output Voltage Stability
      5. 9.1.5 Settling Time and Output Glitch Performance
      6. 9.1.6 Microprocessor Interfacing
        1. 9.1.6.1 DAC8532 to 8051 Interface
        2. 9.1.6.2 DAC8532 to Microwire Interface
        3. 9.1.6.3 DAC8532 to 68HC11 Interface
      7. 9.1.7 DAC8532 to TMS320 DSP Interface
      8. 9.1.8 Bipolar Operation Using the DAC8532
    2. 9.2 Typical Application
      1. 9.2.1 Using REF5050 as a Power Supply for DAC8532
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VDD to GND –0.3 6 V
Digital input voltage to GND –0.3 VDD+0.3
VOUTA or VOUTB to GND –0.3 VDD+0.3
Operating temperature range –40 105 °C
TJ 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 1000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

all specifications –40°C to 105°C (unless otherwise noted)
MIN NOM MAX UNIT
VDD to GND 0 5.5 V
Digital input voltage to GND 0 VDD
VOUTA or VOUTB to GND 0 VDD
Operating temperature range –40 105 °C

7.4 Thermal Information

THERMAL METRIC(1) DAC8532 UNIT
DGK
8 PINS
RθJA Junction-to-ambient thermal resistance 164.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 59.4
RθJB Junction-to-board thermal resistance 84.8
ψJT Junction-to-top characterization parameter 6.5
ψJB Junction-to-board characterization parameter 83.3
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

VDD = 2.7 V to 5.5 V, all specifications –40°C to 105°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
Resolution 16 Bits
Relative accuracy ±0.0987 % of FSR
Differential nonlinearity 16-bit monotonic ±1 LSB
Zero code error 5 25 mV
Full-scale error –0.15 –1 % of FSR
Gain error ±1 % of FSR
Zero code error drift ±20 µV/°C
Gain temperature coefficient ±5 ppm of FSR/°C
Channel-to-channel matching PSRR RL = 2 kΩ, CL = 200 pF 15 mV
0.75 mV/V
OUTPUT CHARACTERISTICS(2)
Output voltage range 0 VREF V
Output voltage settling time To ±0.003% FSR 0200H to FD00H, RL = 2 kΩ;
0 pF < CL < 200 pF, RL = 2 kΩ; CL = 500 pF 		8 10 µs
12
Slew rate 1 V/µs
Capacitive load stability RL = ∞ 470 pF
RL = 2 kΩ 1000
Code change glitch impulse 1 LSB change around major carry 20 nV-s
Digital feedthrough 0.5 nV-s
DC crosstalk 0.25 LSB
AC crosstalk –100 –96 dB
DC output impedance 1 Ω
Short circuit current VDD = 5 V 50 mA
VDD = 3 V 20
Power-up time Coming out of power-down mode VDD = 5 V 2.5 µs
Coming out of power-down mode VDD = 3 V 5 µs
AC PERFORMANCE
SNR BW = 20 kHz, VDD = 5 V, FOUT = 1 kHz,
1st 19 harmonics removed		 94 dB
THD 67
SFDR 69
SINAD 65
REFERENCE INPUT
Reference current VREF = VDD = 5 V 67 90 µA
VREF = VDD = 3 V 40 54
Reference input range 0 VDD V
Reference input impedance 75 kΩ
LOGIC INPUTS (2)
Input current ±1 µA
VINL, Input LOW voltage VDD = 5 V 0.8 V
VDD = 3 V 0.6
VINH, Input HIGH voltage VDD = 5 V 2.4 V
VDD = 3 V 2.1
Pin capacitance 3 pF
POWER REQUIREMENTS
VDD 2.7 5.5 V
IDD (normal mode) DAC active and excluding load current
VDD = 3.6 V to 5.5 V VIH = VDD and VIL = GND 500 800 µA
VDD = 2.7 V to 3.6 V 450 750
IDD (all power-down modes)
VDD = 3.6 V to 5.5 V VIH = VDD and VIL = GND 0.2 1 µA
VDD = 2.7 V to 3.6 V 0.05 1
POWER EFFICIENCY
IOUT/IDD ILOAD = 2 mA, VDD = 5 V 89%
TEMPERATURE RANGE
Specified performance –40 105 °C
(1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded.
(2) Ensured by design and characterization, not production tested.

7.6 Timing Requirements (1)(2)

VDD = 2.7 V to 5.5 V, all specifications –40°C to 105°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1(3) SCLK cycle time VDD = 2.7 V to 3.6 V 50 ns
VDD = 3.6 V to 5.5 V 33
t2 SCLK HIGH time VDD = 2.7 V to 3.6 V 13 ns
VDD = 3.6 V to 5.5 V 13
t3 SCLK LOW time VDD = 2.7 V to 3.6 V 22.5 ns
VDD = 3.6 V to 5.5 V 13
t4 SYNC to SCLK rising edge setup time VDD = 2.7 V to 3.6 V 0 ns
VDD = 3.6 V to 5.5 V 0
t5 Data setup time VDD = 2.7 V to 3.6 V 5 ns
VDD = 3.6 V to 5.5 V 5
t6 Data hold time VDD = 2.7 V to 3.6 V 4.5 ns
VDD = 3.6 V to 5.5 V 4.5
t7 24th SCLK falling edge to SYNC rising edge VDD = 2.7 V to 3.6 V 0 ns
VDD = 3.6 V to 5.5 V 0
t8 Minimum SYNC HIGH time VDD = 2.7 V to 3.6 V 50 ns
VDD = 3.6 V to 5.5 V 33
t9 24th SCLK falling edge to SYNC falling edge VDD = 2.7 V to 5.5 V 100 ns
(1) All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See Serial Write Operation timing diagram Figure 1.
(3) Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.

serial_write2_SBAS246.gifFigure 1. Serial Write Operation

7.7 Typical Characteristics

le_5v_cha_bas246.gif
Figure 2. Linearity Error and
Differential Linearity Error vs Code
le_27v_cha_bas246.gif
Figure 4. Linearity Error and
Differential Linearity Error vs Code
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Figure 6. Zero-Scale Error vs Temperature
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Figure 8. Absolute Error
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Figure 10. Output Voltage Drift
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Figure 12. Histogram of Current Consumption
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Figure 14. Source Current Capability
idd_vdd_digt_bas246.gif
Figure 16. Supply Current vs Digital Input Code
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Figure 18. Supply Current vs Supply Voltage
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Figure 20. Supply Current vs Logic Input Voltage
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Figure 22. Half-Scale Settling Time (Large Signal)
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Figure 24. Half-Scale Settling Time (Large Signal)
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Figure 26. Exiting Power-Down Mode
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Figure 28. Output Glitch (Mid-Scale)
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Figure 30. Total Harmonic Distortion vs Output Frequency
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Figure 3. Linearity Error and
Differential Linearity Error vs Code
le_27v_chb_bas246.gif
Figure 5. Linearity Error and
Differential Linearity Error vs Code
full_v_temp_bas246.gif
Figure 7. Full-Scale Error vs Temperature
abs_27v_err_bas246.gif
Figure 9. Absolute Error
hist_5v_bas246.gif
Figure 11. Histogram of Current Consumption
vo_isink_bas246.gif
Figure 13. Sink Current Capability
vo_27v_isour_bas246.gif
Figure 15. Source Current Capability
idd_v_temp_bas246.gif
Figure 17. Supply Current vs Temperature
pd_idd_vdd_bas246.gif
Figure 19. Power-Down Current vs Supply Voltage
full_5v_tim_bas246.gif
Figure 21. Full-Scale Settling Time (Large Signal)
full_27v_tim_bas246.gif
Figure 23. Full-Scale Settling Time (Large Signal)
pow_on_reset_bas246.gif
Figure 25. Power-On Reset to Zero-Scale
out_glitch_bas246.gif
Figure 27. Output Glitch (Worst Case)
snr_v_freq_bas246.gif
Figure 29. Signal-to-Noise Ratio vs Output Frequency