SLOS861C March   2015  – January 2023 DRV2700

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Boost Converter and Control Loop
      2. 7.3.2 High-Voltage Amplifier
      3. 7.3.3 Fast Start-Up (Enable Pin)
      4. 7.3.4 Gain Control
      5. 7.3.5 Adjustable Boost Voltage
      6. 7.3.6 Adjustable Boost Current-Limit
      7. 7.3.7 Internal Charge Pump
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Boost + Amplifier Mode
      2. 7.4.2 Flyback Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 AC-Coupled DAC Input Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Piezo Load Selection
          2. 8.2.1.2.2  Programming The Boost Voltage
          3. 8.2.1.2.3  Inductor and Transformer Selection
          4. 8.2.1.2.4  Programing the Boost and Flyback Current-Limit
          5. 8.2.1.2.5  Boost Capacitor Selection
          6. 8.2.1.2.6  Pulldown FET and Resistors
          7. 8.2.1.2.7  Low-Voltage Operation
          8. 8.2.1.2.8  Current Consumption Calculation
          9. 8.2.1.2.9  Input Filter Considerations
          10. 8.2.1.2.10 Output Limiting Factors
          11. 8.2.1.2.11 Startup and Shutdown Sequencing
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Filtered AC Coupled Single-Ended PWM Input Application
      3. 8.2.3 DC-Coupled DAC Input Application
      4. 8.2.4 DC-Coupled Reference Input Application
      5. 8.2.5 Flyback Circuit
    3. 8.3 System Example
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Boost + Amplifier Configuration Layout Considerations
      2. 10.1.2 Flyback Configuration Layout Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Flyback Circuit

The flyback circuit is intended for applications using piezo valves, piezo polymers, and other high-voltage loads. The previously listed applications go from ±100 V, however this circuit can go up to even higher voltages (1 kV for example) depending on the feedback network and maximum operating conditions of the external components. The input is controlled using PWM, a DAC, or a purely analog signal. Therefore, a proper input filter may be required as discussed in the previous application circuits.

The increased voltage range, however, comes at a price. As the output voltage increases, the capable output sourcing current is lowered. However, because most piezo loads require a small current for the holding or blocking force, the drop in current may not impact the performance of the application. Figure 8-16 shows a typical flyback circuit.

GUID-14C5D49B-0CF4-4392-8211-446DC8B6AA12-low.svg Figure 8-16 Flyback Circuit

The following sections shown in Figure 8-16 must be explained:

  • Op-amp integrator
  • Comparator and pulldown FET
  • C(HV) value

The op-amp integrator shown at the bottom of the circuit in Figure 8-16, is used to control the output voltage. Because the input can be a PWM or DAC signal, it helps smooth out the input signal. Additionally, the output controls the virtual ground of the feedback network. For example, when the output of the integrator is equal to VOL (approximately 0 V), the current through R(FB2) is at the maximum and therefore increase the current (and voltage) on R(FB1) which raises the voltage across the piezo load. Likewise, as the output voltage of the integrator increases, it then decreases the current through R(FB2) and therefore decreases the voltage on R(FB1), which lowers the voltage across the piezo load.

The comparator and pulldown FET are used to drain the charge on the high-voltage output. Because a high resistance (or low current) is desired through for the feedback network, the RC-time constant of draining charge can be very long. To help with this long RC-time constraint, the comparator and pulldown FET are added to drain charge when VFB > Vref which adds a low resistance in parallel and therefore lowers the RC time constant. Ensure that this pulldown network can support the voltage and the current. As shown in Figure 8-9 and Figure 8-10, the pulldown allows for better regulation and faster stopping time.

Lastly, the C(HV) value is determined by the system. A value of >1-nF total capacitance is required on the high-voltage node for proper regulation. This total capacitance is the combination of the piezo load and the onboard C(HV).

Note:

As the capacitance increases, the voltage ripple on the output decreases. However, this decrease in ripple also slows down the startup or slew rate on the output. Ensure that the C(HV) and the piezo load can support the high voltage across C(HV) and the load.