SLVSDX8B March 2017 – December 2018 DRV8702D-Q1 , DRV8703D-Q1
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Config control is shown in Figure 52 and described in Table 22.
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Read and write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOFF | CHOP_IDS | VREF_SCL | SH_EN | GAIN_CS | |||
R/W-00b | R/W-0b | R/W-00b | R/W-0b | R/W-01b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7-6 | TOFF | R/W | 00b |
Off time for PWM current chopping 00b = 25 µs 01b = 50 µs 10b = 100 µs 11b = 200 µs |
5 | CHOP_IDS | R/W | 0b |
Disables current regulation (enabled by default) |
4-3 | VREF_SCL | R/W | 00b |
Scale factor for the VREF input 00b = 100% 01b = 75% 10b = 50% 11b = 25% |
2 | SH_EN | R/W | 0b |
Enables sample and hold operation of the shunt amplifier (disabled by default) |
1-0 | GAIN_CS | R/W | 01b |
Shunt amplifier gain setting 00b = 10 V/V 01b = 19.8 V/V 10b = 39.4 V/V 11b = 78 V/V |