SLVSD29 October   2015 DRV8704

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Motor Drivers
      2. 7.3.2  Direct PWM Input Mode (Dual Brushed DC Gate Driver)
      3. 7.3.3  Current Regulation
      4. 7.3.4  Decay Modes
      5. 7.3.5  Blanking Time
      6. 7.3.6  Gate Drivers
      7. 7.3.7  Configuring Gate Drivers
      8. 7.3.8  External FET Selection
      9. 7.3.9  Protection Circuits
        1. 7.3.9.1 Overcurrent Protection (OCP)
        2. 7.3.9.2 Gate Driver Fault (PDF)
        3. 7.3.9.3 Thermal Shutdown (TSD)
        4. 7.3.9.4 Undervoltage Lockout (UVLO)
      10. 7.3.10 Serial Data Format
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 Control Registers
        1. 7.5.1.1 CTRL Register (Address = 0x00h)
          1. Table 4. CTRL Register
        2. 7.5.1.2 TORQUE Register (Address = 0x01h)
          1. Table 5. TORQUE Register
        3. 7.5.1.3 OFF Register (Address = 0x02h)
          1. Table 6. OFF Register
        4. 7.5.1.4 BLANK Register (Address = 0x03h)
          1. Table 7. BLANK Register
        5. 7.5.1.5 DECAY Register (Address = 0x04h)
          1. Table 8. DECAY Register
        6. 7.5.1.6 Reserved Register Address = 0x05h
          1. Table 9. Reserved Register
        7. 7.5.1.7 DRIVE Register Address = 0x06h
          1. Table 10. DRIVE Register
        8. 7.5.1.8 STATUS Register (Address = 0x07h)
          1. Table 11. STATUS Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 Current Chopping Configuration
        4. 8.2.2.4 Decay Modes
        5. 8.2.2.5 Sense Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 Blanking Time

After the current is enabled in an H-bridge, the voltage on the ISEN pin is ignored for a period of time before enabling the current sense circuitry. This blanking time is adjustable from 500 ns to 5.14 µs, in 20-ns increments, by setting the TBLANK bits in the BLANK register. Note that the blanking time also sets the minimum drive time of the PWM.

The same blanking time is applied to the fast decay period in auto mixed decay mode. The PWM will ignore any transitions on Itrip after entering fast decay mode, until the blanking time has expired.