SLVSBA3C June   2012  – December 2015 DRV8806

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Drivers
      2. 7.3.2 Protection Circuits
        1. 7.3.2.1 Overcurrent Protection (OCP)
        2. 7.3.2.2 Thermal Shutdown (TSD)
        3. 7.3.2.3 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface Operation
      2. 7.4.2 Fault Output Register
      3. 7.4.3 Daisy-Chain Connection
      4. 7.4.4 nENBL and RESET Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
        2. 8.2.2.2 Drive Current
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
      2. 10.3.2 Heatsinking
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VM Power supply voltage –0.3 43 V
VOUTx Output voltage –0.3 43 V
VCLAMP Clamp voltage –0.3 43 V
SDATOUT,
nFAULT		 Output current 20 mA
Peak clamp diode current(3) 2 A
DC or RMS clamp diode current(3) 1 A
Digital input pin voltage –0.5 7 V
SDATOUT,
nFAULT		 Digital output pin voltage –0.5 7 V
Peak motor drive output current, t < 1 μS Internally limited A
Continuous total power dissipation(3) See Thermal Information
TJ Operating virtual junction temperature(3) –40 150 °C
Tstg Storage temperature –60 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Power dissipation and thermal limits must be observed.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±6000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VM Power supply voltage 8.2 40 V
VCLAMP Output clamp voltage(2) 0 40 V
IOUT Continuous output current, single channel on, TA = 25°C(1) 2 A
Continuous output current, four channels on, TA = 25°C(1) 1 A
(1) Power dissipation and thermal limits must be observed.
(2) VCLAMP is not a power supply input pin - it only connects to the output clamp diodes.

6.4 Thermal Information

THERMAL METRIC(1) DRV8806 UNIT
PWP (HTSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 39.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 24.6 °C/W
RθJB Junction-to-board thermal resistance 20.3 °C/W
ψJT Junction-to-top characterization parameter 0.7 °C/W
ψJB Junction-to-board characterization parameter 20.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TA = 25°C, over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVM VM operating supply current VM = 24 V 1.6 3 mA
VUVLO VM undervoltage lockout voltage VM rising 8.2 V
LOGIC-LEVEL INPUTS (SCHMITT TRIGGER INPUTS WITH HYSTERESIS)
VIL Input low voltage 0.8 V
VIH Input high voltage 2 V
VHYS Input hysteresis 0.45 V
IIL Input low current VIN = 0 –20 20 μA
IIH Input high current VIN = 3.3 V 100 μA
RPD Pulldown resistance 100 kΩ
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL Output low voltage IO = 5 mA 0.5 V
IOH Output high leakage current VO = 3.3 V 1 μA
SDATOUT OUTPUT (PUSH-PULL OUTPUT WITH INTERNAL PULLUP)
VOL Output low voltage IO = 5 mA 0.5 V
VOH Output high voltage IO = 100 µA, VM = 11 V - 60 V, peak 6.5 V
IO = 100 µA, VM = 11 V - 60 V, steady state 3.3 4.5 5.6
IO = 100 µA, VM = 8.2 V - 11 V, steady state 2.5 V
ISRC Output source current VM = 24 V 1 mA
ISNK Output sink current VM = 24 V 5 mA
LOW-SIDE FETS
RDS(ON) FET on resistance VM = 24 V, IO = 700 mA, TJ = 25°C 0.5 Ω
VM = 24 V, IO = 700 mA, TJ = 85°C 0.75 0.8
IOFF Open load detect current 0 25 50 μA
HIGH-SIDE DIODES
VF Diode forward voltage VM = 24 V, IO = 700 mA, TJ = 25°C 0.9 V
IOFF Off state leakage current VM = 24 V, TJ = 25°C –50 50 μA
OUTPUTS
tR Rise time VM = 24 V, IO = 700 mA, Resistive load 50 300 ns
tF Fall time VM = 24 V, IO = 700 mA, Resistive load 50 150 ns
PROTECTION CIRCUITS
IOCP Overcurrent protection trip level 3 5 A
tOCP Overcurrent protection deglitch time 3.5 µs
tOL Open load detect deglitch time 15 µs
tRETRY Overcurrent protection re-try time 1.2 ms
TTSD Thermal shutdown temperature Die temperature 150 160 180 °C

6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
1 tCYC Clock cycle time 62 ns
2 tCLKH Clock high time 25 ns
3 tCLKL Clock low time 25 ns
4 tSU(SDATIN) Setup time, SDATIN to SCLK 5 ns
5 tH(SDATIN) Hold time, SDATIN to SCLK 1 ns
6 tD(SDATOUT) Delay time, SCLK to SDATOUT, no external pullup resistor,
COUT = 100 pF		 50 100 ns
7 tW(LATCH) Pulse width, LATCH 200 ns
8 tOE(ENABLE) Enable time, nENBL to output low 60 ns
9 tD(LATCH) Delay time, LATCH to output change 200 ns
— tRESET RESET pulse width 20 µs
10 tD(RESET) Reset delay before clock 20 µs
11 tSTARTUP Start-up delay VM applied before clock 55 µs
(1) Not production tested.
DRV8806 timing_lvsba3.gif
More than 400 ns of delay should exist between the final SCLK rising edge and the LATCH rising edge. This ensures that the last data bit is shifted into the device properly.
Figure 1. DRV8806 Timing Requirements

6.7 Typical Characteristics

DRV8806 C001_SLVSBA3.png
Figure 2. Supply Current vs Temperature
DRV8806 C004_SLVSBA3.png
Figure 4. RDS(ON) vs Temperature
DRV8806 C002_SLVSBA3.png
Figure 3. Supply Current vs Supply Voltage
DRV8806 C005_SLVSBA3.png
Figure 5. RDS(ON) vs Supply Voltage