SNLS739 October   2023 DS320PR410

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Pin mode
        1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
        1. 7.5.2.1 Shared Registers
        2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe Reach Extension – x16 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNQ|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20230522-SS0I-FFZN-04ML-HRWZVZKMSTGT-low.svg Figure 5-1 RNQ Package,40-Pin WQFN(Top View)
Table 5-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
DONEn7O, 3.3 V open drainIn SMBus/I2C Primary mode:
Indicates the completion of a valid EEPROM register load operation. External pullup resistor such as 4.7 kΩ required for operation.
High: External EEPROM load failed or incomplete
Low: External EEPROM load successful and complete
In SMBus/I2C Secondary/Pin mode:
This output is High-Z. The pin can be left floating.
MODE25I, 5-levelSets device control configuration modes. 5-level IO pin as provided in Table 7-4. The pin can be exercised at device power up or in normal operation mode.
L0: Pin mode – strap pins solely sets device control configuration settings.
L1: SMBus/I2C Primary mode – device control configuration is read from external EEPROM. When the DS320PR410 has finished reading from the EEPROM successfully, it will drive the DONEn pin LOW. SMBus/I2C secondary operation is available in this mode before, during or after EEPROM reading. Note: during EEPROM reading if the external SMBus/I2C primary wants to access DS320PR410 registers it must support arbitration.
L2: SMBus/I2C Secondary mode – an external controller with SMBus/I2C primary sets device control configuration settings.
L3 and L4 (Float): RESERVED – TI internal test modes.
EQ0 / ADDR023I, 5-levelIn Pin mode:
Sets receiver linear equalization (CTLE) boost for channels 0-3 as provided in Table 7-1. These pins are sampled at device power-up only.
In SMBus/I2C mode:
Sets SMBus / I2C secondary address as provided in Table 7-5. These pins are sampled at device power-up only. In this mode, equalization boost is configured by setting SMBus / I2C register bits.
EQ1 / ADDR124I, 5-level
GAIN / SDA27I, 5-level / I/O, 3.3 V LVCMOS, open drainIn Pin mode:
Flat gain (DC and AC) from the input to the output of the device for channels 0-3. The pin is sampled at device power-up only.
In SMBus/I2C mode:
3.3 V SMBus/I2C data. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus / I2C interface standard. In this mode, Flat gain is configured by setting SMBus / I2C register bits.
GND1, 8, 11, 18, 21, 28, 31, 38, EPPGround reference for the device.
EP: the Exposed Pad at the bottom of the QFN package. It is used as the GND return for the device. The EP should be connected to one or more ground planes through the low resistance path. A via array provides a low impedance path to GND. The EP also improves thermal dissipation.
PD6I, 3.3 V LVCMOS2-level logic controlling the operating state of the redriver. Active in all device control modes. The pin has internal 1-MΩ weak pull-down resistor. The pin triggers PCIe Rx detect state machine when toggled.
High: power down for channels 0-3
Low: power up, normal operation for channels 0-3
READ_EN_N22I, 3.3 V LVCMOSIn SMBus/I2C Primary mode:
After device power up, when the pin is low, the pin initiates the SMBus / I2C Primary mode EEPROM read function. When EEPROM read is complete (indicated by assertion of DONEn low), this pin can be held low for normal device operation. During the EEPROM load process the device’s signal path is disabled.
In SMBus/I2C Secondary and Pin modes:
In these modes the pin is not used. The pin can be left floating. The pin has internal 1-MΩ weak pull-down resistor.
RSVD2—Reserved use for TI. The pin must be left floating (NC).
RX_DET / SCL26I, 5-level / I/O, 3.3 V LVCMOS, open drainIn Pin mode:
Sets receiver detect state machine options as provided in Table 7-3. The pin is sampled at device power-up only.
In SMBus/I2C mode:
3.3V SMBus/I2C clock. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus / I2C interface standard. In this mode, receiver detect state machine is configured by setting SMBus / I2C register bits.
RX0N30IInverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 0.
RX0P29INon-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 0.
RX1N33IInverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 1.
RX1P32INon-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 1.
RX2N37IInverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 2.
RX2P36INon-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 2.
RX3N40IInverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 3.
RX3P39INon-inverting differential inputs to the equalizer. Integrated 50 Ω termination resistor from the pin to internal CM bias voltage. Channel 3.
TX0N19OInverting pin for 100 Ω differential driver output. Channel 0.
TX0P20ONon-inverting pin for 100 Ω differential driver output. Channel 0.
TX1N16OInverting pin for 100 Ω differential driver output. Channel 1.
TX1P17ONon-inverting pin for 100 Ω differential driver output. Channel 1.
TX2N12OInverting pin for 100 Ω differential driver output. Channel 2.
TX2P13ONon-inverting pin for 100 Ω differential driver output. Channel 2.
TX3N9OInverting pin for 100 Ω differential driver output. Channel 3.
TX3P10ONon-inverting pin for 100 Ω differential driver output. Channel 3.
VCC14, 15, 34, 35PPower supply pins. VCC = 3.3 V ±10%. The VCC pins on this device should be connected through a low-resistance path to the board VCC plane. Install a decoupling capacitor to GND near each VCC pin.
(1) I = input, O = output, P = power