SNLS500A July   2016  – January 2024 DS90UB964-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings – JEDEC
    3. 4.3  ESD Ratings – IEC and ISO
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Thermal Information
    6. 4.6  DC Electrical Characteristics
    7. 4.7  AC Electrical Characteristics
    8. 4.8  Recommended Timing for the Serial Control Bus
    9. 4.9  AC Electrical Characteristics
    10. 4.10 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
    4. 5.4 Device Functional Modes
      1. 5.4.1  RAW Data Type Support and Rates
      2. 5.4.2  MODE Pin
      3. 5.4.3  REFCLK
      4. 5.4.4  Receiver Port Control
      5. 5.4.5  Input Jitter Tolerance
      6. 5.4.6  Adaptive Equalizer
        1. 5.4.6.1 Channel Requirements
        2. 5.4.6.2 Adaptive Equalizer Algorithm
        3. 5.4.6.3 AEQ Settings
          1. 5.4.6.3.1 AEQ Start-Up and Initialization
          2. 5.4.6.3.2 AEQ Range
          3. 5.4.6.3.3 AEQ Timing
          4. 5.4.6.3.4 AEQ Threshold
      7. 5.4.7  Channel Monitor Loop-Through Output Driver
        1. 5.4.7.1 Code Example for CMLOUT FPD3 RX Port 0:
      8. 5.4.8  RX Port Status
        1. 5.4.8.1 RX Parity Status
        2. 5.4.8.2 FPD-Link Decoder Status
        3. 5.4.8.3 RX Port Input Signal Detection
      9. 5.4.9  GPIO Support
        1. 5.4.9.1 GPIO Input Control and Status
        2. 5.4.9.2 GPIO Output Pin Control
        3. 5.4.9.3 Back Channel GPIO
        4. 5.4.9.4 GPIO Pin Status
        5. 5.4.9.5 Other GPIO Pin Controls
      10. 5.4.10 RAW Mode LV / FV Controls
      11. 5.4.11 Video Stream Forwarding
      12. 5.4.12 CSI-2 Protocol Layer
      13. 5.4.13 CSI-2 Short Packet
      14. 5.4.14 CSI-2 Long Packet
      15. 5.4.15 CSI-2 Data Identifier
      16. 5.4.16 Virtual Channel and Context
      17. 5.4.17 CSI-2 Mode Virtual Channel Mapping
        1. 5.4.17.1 Example 1
        2. 5.4.17.2 Example 2
      18. 5.4.18 CSI-2 Transmitter Frequency
      19. 5.4.19 CSI-2 Transmitter Status
      20. 5.4.20 Video Buffers
      21. 5.4.21 CSI-2 Line Count and Line Length
      22. 5.4.22 FrameSync Operation
        1. 5.4.22.1 External FrameSync Control
        2. 5.4.22.2 Internally Generated FrameSync
          1. 5.4.22.2.1 Code Example for Internally Generated FrameSync
      23. 5.4.23 CSI-2 Forwarding
        1. 5.4.23.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 5.4.23.2 Synchronized CSI-2 Forwarding
        3. 5.4.23.3 Basic Synchronized CSI-2 Forwarding
          1. 5.4.23.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 5.4.23.4 Line-Interleaved CSI-2 Forwarding
          1. 5.4.23.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 5.4.23.5 Line-Concatenated CSI-2 Forwarding
          1. 5.4.23.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 5.4.23.6 CSI-2 Replicate Mode
        7. 5.4.23.7 CSI-2 Transmitter Output Control
        8. 5.4.23.8 Enabling and Disabling CSI-2 Transmitters
    5. 5.5 Programming
      1. 5.5.1  Serial Control Bus
      2. 5.5.2  Second I2C Port
      3. 5.5.3  I2C Target Operation
      4. 5.5.4  Remote Target Operation
      5. 5.5.5  Remote Target Addressing
      6. 5.5.6  Broadcast Write to Remote Devices
        1. 5.5.6.1 Code Example for Broadcast Write
      7. 5.5.7  I2C Proxy Controller
      8. 5.5.8  I2C Proxy Controller Timing
        1. 5.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 5.5.9  Interrupt Support
        1. 5.5.9.1 Code Example to Enable Interrupts
        2. 5.5.9.2 FPD-Link III Receive Port Interrupts
        3. 5.5.9.3 Code Example to Readback Interrupts
        4. 5.5.9.4 CSI-2 Transmit Port Interrupts
      10. 5.5.10 Timestamp – Video Skew Detection
      11. 5.5.11 Pattern Generation
        1. 5.5.11.1 Reference Color Bar Pattern
        2. 5.5.11.2 Fixed Color Patterns
        3. 5.5.11.3 Pattern Generator Programming
          1. 5.5.11.3.1 Determining Color Bar Size
        4. 5.5.11.4 Code Example for Pattern Generator
      12. 5.5.12 FPD-Link BIST Mode
        1. 5.5.12.1 BIST Operation
    6. 5.6 Register Maps
      1. 5.6.1 Main_Page Registers
      2. 5.6.2 Indirect Access Registers
        1. 5.6.2.1 PATGEN_And_CSI-2 Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power-Over-Coax
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curves
    3. 6.3 System Examples
    4. 6.4 Power Supply Recommendations
      1. 6.4.1 VDD Power Supply
      2. 6.4.2 Power-Up Sequencing
        1. 6.4.2.1 PDB Pin
    5. 6.5 Layout
      1. 6.5.1 Layout Guidelines
        1. 6.5.1.1 Ground
        2. 6.5.1.2 Routing FPD-Link III Signal Traces and PoC Filter
        3. 6.5.1.3 CSI-2 Guidelines
      2. 6.5.2 Layout Example
  9. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 Support Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.6 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS PIN OR FREQUENCY MIN TYP MAX UNIT
1.8 V LVCMOS I/O
(VDDIO = 1.8 V ± 5%)
VIH High Level Input Voltage GPIO[7:0], PDB, REFCLK 0.65 ×
VDDIO		 VDDIO V
VIL Low Level Input Voltage GND 0.35 ×
VDDIO		 V
IIH Input High Current VIN = 0 V or VDDIO Internal Pulldown Enabled GPIO[7:0](1), PDB –20 150 μA
IIH Input High Current VIN = 0 V or VDDIO Internal Pulldown Disabled GPIO[7:0](1) –20 20 μA
IIL Input Low Current VIN = 0 V or VDDIO GPIO[7:0](1), PDB
–20

 20 μA
VOH High Level Output Voltage IOH = –2 mA GPIO[7:0] VDDIO – 0.45 VDDIO V
VOL Low Level Output Voltage IOL = 2 mA GPIO[7:0], INTB GND 0.45 V
IOS Output Short Circuit Current VOUT = 0 V GPIO[7:0] –35 mA
IOZ TRI-STATE Output Current VOUT = 0 V or VDDIO, PDB = LOW GPIO[7:0] –20 20 μA
3.3 V LVCMOS I/O
(VDDIO = 3.3 V ± 10%)
VIH High Level Input Voltage GPIO[7:0] 2 VDDIO V
VIH REFCLK, PDB 1.17 VDDIO
VIL Low Level Input Voltage GPIO[7:0] GND 0.8 V
VIL REFCLK, PDB GND 0.63
IIH Input High Current VIN = 0 V or VDDIO Internal Pulldown Enabled GPIO[7:0](1), PDB –20 200 μA
IIH Input High current VIN = 0 V or VDDIO Internal Pulldown Disabled GPIO[7:0](1) –20 20 μA
IIL Input Low current  VIN = 0 V or VDDIO GPIO[7:0](1), PDB –20 20 μA
VOH High Level Output Voltage IOH = –4 mA GPIO[7:0] 2.4 VDDIO V
VOL Low Level Output Voltage IOL = 4 mA GPIO[7:0], INTB GND 0.4 V
IOS Output Short Circuit Current VOUT = 0 V GPIO[7:0] –50 mA
IOZ TRI-STATE Output Current VOUT = 0 V or VDDIO, PDB = LOW GPIO[7:0] –20 20 μA
I2C SERIAL CONTROL BUS (VDDIO = 1.8 V ± 5%
OR 3.3 V ± 10%)
VIH Input High Level I2C_SDA, I2C_SCL
I2C_SDA2, I2C_SCL2		 0.7 × VDDIO VDDIO V
VIL Input Low Level GND 0.3 × VDDIO V
VHY Input Hysteresis >50 mV
VOL Output Low Level IOL = 4 mA Standard-mode
Fast-mode		 0 0.4 V
IOL = 15 mA Fast-mode Plus 0 0.4 V
IIN Input Current VIN = 0 V or VDDIO –10 10 µA
FPD-LINK III
RECEIVER INPUT
VIN Single-ended Input Voltage  (Figure 5-2) RIN0±, RIN1±,
RIN2±, RIN3±		 60 mV
VID Differential Input Voltage (Figure 5-2) RIN0±, RIN1±,
RIN2±, RIN3±		 115 mV
VCM Common Mode Voltage 1.0 V
IIZ Power-down input current PDB = LOW –10 –10 μA
RT Internal Termination Resistance Single-ended RIN+ or RIN- 40 50 60 Ω
Differential across RIN+ and RIN- 80 100 120 Ω
FPD-LINK III
BI-DIRECTIONAL CONTROL CHANNEL
VOUT-BC Back Channel Single-Ended Output Voltage RL = 50 Ω
Coaxial configuration
Forward channel disabled		 RIN0+, RIN1+
RIN2+, RIN3+		 +190 +220 +260 mV
RIN0-, RIN1-
RIN2-, RIN3-		 –190 –220 –260
VOD-BC Back Channel Differential Output Voltage (RIN+) - (RIN-) RL = 100 Ω
STP configuration
Forward channel disabled		 RIN0±,
RIN1±,
RIN2±,
RIN3±		 380 440 520 mV
HSTX DRIVER
VCMTX HS transmit static common-mode voltage CSI0_D[3:0]P/N,
CSI0_CLKP/N,
CSI1_D[3:0]P/N,
CSI1_CLKP/N		 150 200 250 mV
|ΔVCMTX(1,0)| VCMTX mismatch when output is 1 or 0 5 mVP-P
|VOD| HS transmit differential voltage 140 200 270 mV
|ΔVOD| VOD mismatch when output is 1 or 0 14 mV
VOHHS HS output high voltage 360 mV
ZOS Single-ended output impedance 40 50 62.5 Ω
ΔZOS Mismatch in single-ended output impedance 10 %
LPTX DRIVER
VOH High Level Output Voltage IOH = –4 mA CSI0_D[3:0]P/N,
CSI0_CLKP/N,
CSI1_D[3:0]P/N,
CSI1_CLKP/N		 1.1 1.2 1.3 V
VOL Low Level Output Voltage IOL = 4 mA –50 50 mV
ZOLP Output impedance 110 Ω
POWER CONSUMPTION
PT Total Power Consumption in Operation Mode CSI-2 data rate = 1.6Gbps
4 × FPD-Link III RX inputs
CSI-2 TX = 2 × (4 data lanes + 1 CLK lane)
<Non-Replicate>
Default registers		 1100 mW
SUPPLY CURRENT
IDDT1 DPHY TX Supply Current (includes load current) CSI-2 data rate = 800 Mbps
4 × FPD-Link III RX inputs
CSI-2 TX = 1 data lanes + 1 CLK lane
<Non-Replicate>
Default registers		 VDD11 90 275 mA
VDD18 177 240
VDDIO 10 50
CSI-2 data rate = 1.6Gbps
4 × FPD-Link III RX inputs
CSI-2 TX = 1 data lanes + 1 CLK lane
<Non-Replicate>
Default registers		 VDD11 100 280 mA
VDD18 177 240
VDDIO 10 50
IDDT2 DPHY TX Supply Current (includes load current) CSI-2 data rate = 800 Mbps
4 × FPD-Link III RX inputs
CSI-2 TX = 2 × (4 data lanes + 1 CLK lane)
<Replicate Mode>
Default registers		 VDD11 105 285 mA
VDD18 180 240
VDDIO 10 50
CSI-2 data rate = 1.6Gbps
4 × FPD-Link III RX inputs
CSI-2 TX = 2 × (4 data lanes + 1 CLK lane)
<Replicate Mode>
Default registers		 VDD11 120 380 mA
VDD18 180 240
VDDIO 10 50
IDDZ Standby Current PDB = LOW VDD11 100 mA
VDD18 1
VDDIO 3
(1) GPIO[7:0] Register 0xBE = 0xFF