SLLS983L June   2009  – October 2023 ISO1050

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics - DC Specification
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CAN Bus States
      2. 8.3.2 Digital Inputs and Outputs
      3. 8.3.3 Protection Features
        1. 8.3.3.1 TXD Dominant Time-Out (DTO)
        2. 8.3.3.2 Thermal Shutdown
        3. 8.3.3.3 Undervoltage Lockout and Fail-Safe
        4. 8.3.3.4 Floating Pins
        5. 8.3.3.5 CAN Bus Short-Circuit Current Limiting
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bus Loading, Length and Number of Nodes
        2. 9.2.2.2 CAN Termination
      3. 9.2.3 Application Curve
  11. 10Power Supply Recommendations
    1. 10.1 General Recommendations
    2. 10.2 Power Supply Discharging
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFICATIONS UNIT
DUB-8 DW-16
IEC 60664-1
CLR External clearance(1) Side 1 to side 2 distance through air >6.1 >8 mm
CPG External Creepage(1) Side 1 to side 2 distance across package surface >6.8 >8 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >13.5 >13.5 µm
CTI Comparative tracking index IEC 60112; UL 746A >600 >600 V
Material Group According to IEC 60664-1 I I
Overvoltage category Rated mains voltage ≤ 150 VRMS I-IV I-IV
Rated mains voltage ≤ 300 VRMS I-III I-III
Rated mains voltage ≤ 600 VRMS n/a I-II
Rated mains voltage ≤ 848 VRMS n/a
I
DIN V VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 560 1200 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; 395 848 VRMS
DC voltage 560 1200 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM , t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) 4000 4000 VPK
VIOSM Maximum surge isolation voltage(3) Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.6 x VIOSM = 6.4 kVPK (qualification) 4000 4000 VPK
qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s ≤ 5 ≤ 5 pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.3 × VIORM , tm = 10 s		 ≤ 5 ≤ 5
Method b: At routine test (100% production)  Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.5 x VIORM, tm = 1 s		 ≤ 5 ≤ 5
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2 πft), f = 1 MHz 1 1 pF
RIO Insulation resistance, input to output(5) VIO = 500 V,  TA = 25°C > 1012 > 1012 Ω
VIO = 500 V,  100°C ≤ TA ≤ 150°C > 1011 > 1011
VIO = 500 V at  TS = 150°C > 109 > 109
Pollution degree 2 2
Climatic category 40/125/
21		 40/125/
21
UL 1577
VISO Withstand isolation voltage VTEST = VISO , t = 60 s (qualification); VTEST = 1.2 × VISO , t = 1 s (100% production) 2500 4243 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) ISO1044 is suitable for basic electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.