SNVS325E January   2005  – January 2016 LM2852

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Efficiency vs ILOAD
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 LM2852Y Typical Characteristics (500 kHz)
    7. 6.7 LM2852X Typical Characteristics (1500 kHz)
    8. 6.8 LM2852 Typical Characteristics (Both Y and X Versions)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Split-Rail Operation
      2. 7.3.2 Switch Node Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor (CIN)
        2. 8.2.2.2 Soft-Start Capacitor (CSS)
        3. 8.2.2.3 Soft-Start Capacitor (CSS) and Fault Conditions
        4. 8.2.2.4 Compensation
        5. 8.2.2.5 Output Filter Values
        6. 8.2.2.6 Choosing an Inductance Value
        7. 8.2.2.7 Output Filter Inductors
        8. 8.2.2.8 Output Filter Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PWP Package
14-Pin HTSSOP
Top View
LM2852 20127003.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AVIN 1 I Chip bias input pin. This provides power to the logic of the chip. Connect to the input voltage or a separate rail.
EN 2 I Enable. Connect this pin to ground to disable the chip; connect to AVIN or leave floating to enable the chip; enable is internally pulled up.
Exposed Connect to ground.
NC 5, 12, 13 No connect. These pins must be tied to ground or left floating in the application.
PGND 10, 11 G Power ground. Connect this to an internal ground plane or other large ground plane.
PVIN 6, 7 I Input supply pin. PVIN is connected to the input voltage. This rail connects to the source of the internal power PFET.
SGND 3 G Signal ground.
SNS 14 O Output voltage sense pin. Connect this pin to the output voltage as close to the load as possible.
SS 4 I Soft-start pin. Connect this pin to a small capacitor to control startup. The soft-start capacitance range is restricted to values 1 nF to 50 nF.
SW 8, 9 O Switch pin. Connect to the output inductor.