SNVS808C May   2012  – Februrary 2016 LM5134

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input-to-Output Logic
        2. 8.2.2.2 Input Threshold Type
        3. 8.2.2.3 VDD Bias Supply Voltage
        4. 8.2.2.4 Peak Source and Sink Currents
        5. 8.2.2.5 Enable and Disable Function
        6. 8.2.2.6 Propagation Delay
        7. 8.2.2.7 PILOT MOSFET Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DBV Package, NGG Package
6-Pin SOT-23, 6-Pin WSON
Top View
LM5134 30192802.gif

Pin Functions

PIN I/O DESCRIPTION APPLICATION INFORMATION
NAME NO.
VDD 1 — Gate drive supply Locally decouple to VSS using low ESR/ESL capacitor located as close as possible to the IC.
PILOT 2 O Gate drive output for an external turnoff FET Connect to the gate of a small turnoff MOSFET with a short, low inductance path. The turnoff FET provides a local turnoff path.
OUT 3 O Gate drive output for the power FET Connect to the gate of the power FET with a short, low inductance path. A gate resistor can be used to eliminate potential gate oscillations.
VSS 4 — Ground All signals are referenced to this ground.
INB 5 I Inverting logic input Connect to VSS when not used.
IN 6 I Non-inverting logic input Connect to VDD when not used.
EP EP — Exposed Pad It is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PC board, and that ground plane extend out from beneath the IC to help dissipate heat.