SDLS967H may   2016  – july 2023 LSF0108-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information (Q1)
    5. 6.5 Electrical Characteristics - RKS Package
    6. 6.6 Electrical Characteristics - PW Package
    7. 6.7 Switching Characteristics (Translating Down)
    8. 6.8 Switching Characteristics (Translating Up)
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Auto Bidirectional Voltage Translation
      2. 8.3.2 Output Enable
      3. 8.3.3 Wettable Flanks
    4. 8.4 Device Functional Modes
      1. 8.4.1 Up and Down Translation
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 I2C PMBus, SMBus, GPIO
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
          2. 9.2.1.1.2 Bias Circuitry
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bidirectional Translation
          2. 9.2.1.2.2 Pull-Up Resistor Sizing
          3. 9.2.1.2.3 LSF0108-Q1 Bandwidth
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Mixed-Mode Voltage Translation
        1. 9.2.2.1 Single Supply Translation
        2. 9.2.2.2 Voltage Translation for Vref_B < Vref_A + 0.8 V
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.1.2.3 LSF0108-Q1 Bandwidth

The maximum frequency of the LSF0108-Q1 is dependent on the application. The device can operate at speeds of >100 MHz given the correct conditions. The maximum frequency is dependent upon the loading of the application. The LSF0108-Q1 behaves like a standard switch where the bandwidth of the device is dictated by the on resistance and on capacitance of the device.

Figure 9-3 shows a bandwidth measurement of the LSF0108-Q1 using a two-port network analyzer.

GUID-62694FB9-1618-4F46-BE3C-585E26AEB6FC-low.gif Figure 9-3 3-dB Bandwidth

The 3-dB point of the LSF0108-Q1 is ≅ 600 MHz; however, this measurement is an analog type of measurement. For digital applications the signal should not degrade up to the fifth harmonic of the digital signal. The frequency bandwidth should be at least five times the maximum digital clock rate. This component of the signal is very important in determining the overall shape of the digital signal. In the case of the LSF0108-Q1, a digital clock frequency of greater than 100 MHz can be achieved.

The LSF0108-Q1 does not provide any drive capability. Therefore higher frequency applications will require higher drive strength from the host side. No pull-up resistor is needed on the host side (3.3 V) if the LSF0108-Q1 is being driven by standard CMOS totem pole output driver. Ideally, it is best to minimize the trace length from the LSF0108-Q1 on the sink side (1.8 V) to minimize signal degradation.

All fast edges have an infinite spectrum of frequency components; however, there is an inflection (or knee) in the frequency spectrum of fast edges where frequency components higher than ƒknee are insignificant in determining the shape of the signal.

To calculate the maximum practical frequency component, or the knee frequency (fknee), use Equation 4 and Equation 5:

Equation 4. f k n e e   =   0.5 R T   ( 10   -   80 % )  
Equation 5. f k n e e   =   0.4 R T   ( 20   -   80 % )  

For signals with rise time characteristics based on 10% to 90% thresholds, fknee is equal to 0.5 divided by the rise time of the signal. For signals with rise time characteristics based on 20% to 80% thresholds, which is very common in many of today's device specifications, ƒknee is equal to 0.4 divided by the rise time of the signal.

Some guidelines to follow that will help maximize the performance of the device:

  • Keep trace length to a minimum by placing the LSF0108-Q1 close to the I2C output of the processor.
  • The trace length should be less than half the time of flight to reduce ringing and line reflections or non-monotonic behavior in the switching region.
  • To reduce overshoots, a pull-up resistor can be added on the 1.8 V side; be aware that a slower fall time is to be expected.