SCPS146G October   2005  – March 2021 PCA9544A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Interrupt Timing Requirements
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
    6. 8.6 Register Map
      1. 8.6.1 Control Register
        1. 8.6.1.1 Device Address
        2. 8.6.1.2 Control Register Description
        3. 8.6.1.3 Control Register Definition
        4. 8.6.1.4 Interrupt Handling
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The PCA9544A is a 4-channel, bidirectional translating multiplexer controlled via the I2C bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. One SCL/SDA pair can be selected at a time, and this is determined by the contents of the programmable control register. Four interrupt inputs ( INT3– INT0), one for each of the downstream pairs, are provided. One interrupt output ( INT) acts as an AND of the four interrupt inputs.

A power-on reset function puts the registers in their default state and initializes the I2C state machine, with no channel selected.

The pass gates of the switches are constructed such that the VCC pin can be used to limit the maximum high voltage, which will be passed by the PCA9544A. This allows the use of different bus voltages on each pair, so that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts, without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5-V tolerant.

Device Information
PART NUMBERPACKAGE(1)BODY SIZE (NOM)
PCA9544ATVSOP (DGV) (20)5.00 mm x 4.40 mm
SOIC (DW) (20)12.8 mm x 7.50 mm
TSSOP (PW) (20)6.50 mm × 4.40 mm
VQFN (RGY) (20)4.50 mm x 3.50 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-358CC0C3-11AA-46A9-AEF9-F7EB9B825543-low.gif Simplified Application Diagram