SLDS216 December   2017 PGA302

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Overvoltage and Reverse Voltage Protection
    6. 7.6  Linear Regulators
    7. 7.7  Internal Reference
    8. 7.8  Internal Oscillator
    9. 7.9  Bridge Sensor Supply
    10. 7.10 Temperature Sensor Supply
    11. 7.11 Bridge Offset Cancel
    12. 7.12 P Gain and T Gain Input Amplifiers (Chopper Stabilized)
    13. 7.13 Analog-to-Digital Converter
    14. 7.14 Internal Temperature Sensor
    15. 7.15 Bridge Current Measurement
    16. 7.16 One Wire Interface
    17. 7.17 DAC Output
    18. 7.18 DAC Gain for DAC Output
    19. 7.19 Non-Volatile Memory
    20. 7.20 Diagnostics - PGA30x
    21. 7.21 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Overvoltage and Reverse Voltage Protection
      2. 8.3.2  Linear Regulators
      3. 8.3.3  Internal Reference
      4. 8.3.4  Internal Oscillator
      5. 8.3.5  VBRGP and VBRGN Supply for Resistive Bridge
      6. 8.3.6  ITEMP Supply for Temperature Sensor
      7. 8.3.7  P Gain
      8. 8.3.8  T Gain
      9. 8.3.9  Bridge Offset Cancel
      10. 8.3.10 Analog-to-Digital Converter
        1. 8.3.10.1 Sigma Delta Modulator for ADC
        2. 8.3.10.2 Decimation Filter for ADC
        3. 8.3.10.3 Internal Temperature Sensor ADC Conversion
        4. 8.3.10.4 ADC Scan Mode
          1. 8.3.10.4.1 P-T Multiplexer Timing in Auto Scan Mode
      11. 8.3.11 Internal Temperature Sensor
      12. 8.3.12 Bridge Current Measurement
      13. 8.3.13 Digital Interface
      14. 8.3.14 OWI
        1. 8.3.14.1 Overview of OWI Interface
        2. 8.3.14.2 Activating and Deactivating the OWI Interface
          1. 8.3.14.2.1 Activating OWI Communication
          2. 8.3.14.2.2 Deactivating OWI Communication
        3. 8.3.14.3 OWI Protocol
          1. 8.3.14.3.1 OWI Frame Structure
            1. 8.3.14.3.1.1 Standard field structure:
            2. 8.3.14.3.1.2 Frame Structure
            3. 8.3.14.3.1.3 Sync Field
            4. 8.3.14.3.1.4 Command Field
            5. 8.3.14.3.1.5 Data Field(s)
          2. 8.3.14.3.2 OWI Commands
            1. 8.3.14.3.2.1 OWI Write Command
            2. 8.3.14.3.2.2 OWI Read Initialization Command
            3. 8.3.14.3.2.3 OWI Read Response Command
            4. 8.3.14.3.2.4 OWI Burst Write Command (EEPROM Cache Access)
            5. 8.3.14.3.2.5 OWI Burst Read Command (EEPROM Cache Access)
          3. 8.3.14.3.3 OWI Operations
            1. 8.3.14.3.3.1 Write Operation
            2. 8.3.14.3.3.2 Read Operation
            3. 8.3.14.3.3.3 EEPROM Burst Write
            4. 8.3.14.3.3.4 EEPROM Burst Read
        4. 8.3.14.4 OWI Communication Error Status
      15. 8.3.15 I2C Interface
        1. 8.3.15.1 Overview of I2C Interface
        2. 8.3.15.2 I2C Interface Protocol
        3. 8.3.15.3 Clocking Details of I2C Interface
      16. 8.3.16 DAC Output
      17. 8.3.17 DAC Gain for DAC Output
        1. 8.3.17.1 Connecting DAC Output to DAC GAIN Input
      18. 8.3.18 Memory
        1. 8.3.18.1 EEPROM Memory
          1. 8.3.18.1.1 EEPROM Cache
          2. 8.3.18.1.2 EEPROM Programming Procedure
          3. 8.3.18.1.3 EEPROM Programming Current
          4. 8.3.18.1.4 CRC
      19. 8.3.19 Diagnostics
        1. 8.3.19.1 Power Supply Diagnostics
        2. 8.3.19.2 Sensor Connectivity/Gain Input Faults
        3. 8.3.19.3 Gain Output Diagnostics
        4. 8.3.19.4 PGA302 Harness Open Wire Diagnostics
        5. 8.3.19.5 EEPROM CRC and TRIM Error
      20. 8.3.20 Digital Compensation and Filter
        1. 8.3.20.1 Digital Gain and Offset
        2. 8.3.20.2 TC and NL Correction
        3. 8.3.20.3 Clamping
        4. 8.3.20.4 Filter
      21. 8.3.21 Revision ID
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
      1. 8.5.1 Programmer's Model
        1. 8.5.1.1 Memory Map
        2. 8.5.1.2 Control and Status Registers
          1. 8.5.1.2.1  MICRO_INTERFACE_CONTROL (DI Page Address = 0x0) (DI Page Offset = 0x0C)
          2. 8.5.1.2.2  PSMON1 (M0 Address= 0x40000558) (DI Page Address = 0x2) (DI Page Offset = 0x58)
          3. 8.5.1.2.3  AFEDIAG (M0 Address= 0x4000055A) (DI Page Address = 0x2) (DI Page Offset = 0x5A)
          4. 8.5.1.2.4  P_GAIN_SELECT (DI Page Address = 0x2) (DI Page Offset = 0x47)
          5. 8.5.1.2.5  T_GAIN_SELECT (DI Page Address = 0x2) (DI Page Offset = 0x48)
          6. 8.5.1.2.6  TEMP_CTRL (DI Page Address = 0x2) (DI Page Offset = 0x4C)
          7. 8.5.1.2.7  OFFSET_CANCEL (DI Page Address = 0x2) (DI Page Offset = 0x4E)
          8. 8.5.1.2.8  PADC_DATA1 (DI Page Address = 0x0) (DI Page Offset = 0x10)
          9. 8.5.1.2.9  PADC_DATA2 (DI Page Address = 0x0) (DI Page Offset = 0x11)
          10. 8.5.1.2.10 TADC_DATA1 (DI Page Address = 0x0) (DI Page Offset = 0x14)
          11. 8.5.1.2.11 TADC_DATA2 (DI Page Address = 0x0) (DI Page Offset = 0x15)
          12. 8.5.1.2.12 DAC_REG0_1 (DI Page Address = 0x2) (DI Page Offset = 0x30)
          13. 8.5.1.2.13 DAC_REG0_2 (DI Page Address = 0x2) (DI Page Offset = 0x31)
          14. 8.5.1.2.14 OP_STAGE_CTRL (DI Page Address = 0x2) (DI Page Offset = 0x3B)
          15. 8.5.1.2.15 EEPROM_ARRAY (DI Page Address = 0x5) (DI Page Offset = 0x00 - 0x7F)
          16. 8.5.1.2.16 EEPROM_CACHE_BYTE0 (DI Page Address = 0x5) (DI Page Offset = 0x80)
          17. 8.5.1.2.17 EEPROM_CACHE_BYTE1 (DI Page Address = 0x5) (DI Page Offset = 0x81)
          18. 8.5.1.2.18 EEPROM_PAGE_ADDRESS (DI Page Address = 0x5) (DI Page Offset = 0x82)
          19. 8.5.1.2.19 EEPROM_CTRL (DI Page Address = 0x5) (DI Page Offset = 0x83)
          20. 8.5.1.2.20 EEPROM_CRC (DI Page Address = 0x5) (DI Page Offset = 0x84)
          21. 8.5.1.2.21 EEPROM_STATUS (DI Page Address = 0x5) (DI Page Offset = 0x85)
          22. 8.5.1.2.22 EEPROM_CRC_STATUS (DI Page Address = 0x5) (DI Page Offset = 0x86)
          23. 8.5.1.2.23 EEPROM_CRC_VALUE (DI Page Address = 0x5) (DI Page Offset = 0x87)
          24. 8.5.1.2.24 H0 (EEPROM Address= 0x40000000)
          25. 8.5.1.2.25 H1 (EEPROM Address= 0x40000002)
          26. 8.5.1.2.26 H2 (EEPROM Address= 0x40000004)
          27. 8.5.1.2.27 H3 (EEPROM Address= 0x40000006)
          28. 8.5.1.2.28 G0 (EEPROM Address= 0x40000008)
          29. 8.5.1.2.29 G1 (EEPROM Address= 0x4000000A)
          30. 8.5.1.2.30 G2 (EEPROM Address= 0x4000000C)
          31. 8.5.1.2.31 G3 (EEPROM Address= 0x4000000E)
          32. 8.5.1.2.32 N0 (EEPROM Address= 0x40000010)
          33. 8.5.1.2.33 N1 (EEPROM Address= 0x40000012)
          34. 8.5.1.2.34 N2 (EEPROM Address= 0x40000014)
          35. 8.5.1.2.35 N3 (EEPROM Address= 0x40000016)
          36. 8.5.1.2.36 M0 (EEPROM Address= 0x40000018)
          37. 8.5.1.2.37 M1 (EEPROM Address= 0x4000001A)
          38. 8.5.1.2.38 M2 (EEPROM Address= 0x4000001C)
          39. 8.5.1.2.39 M3 (EEPROM Address= 0x4000001E)
          40. 8.5.1.2.40 PADC_GAIN (EEPROM Address= 0x40000020)
          41. 8.5.1.2.41 TADC_GAIN (EEPROM Address= 0x40000021)
          42. 8.5.1.2.42 PADC_OFFSET (EEPROM Address= 0x40000022)
          43. 8.5.1.2.43 TADC_OFFSET (EEPROM Address= 0x40000024)
          44. 8.5.1.2.44 TEMP_SW_CTRL (EEPROM Address= 0x40000028)
          45. 8.5.1.2.45 DAC_FAULT_MSB (EEPROM Address= 0x4000002A)
          46. 8.5.1.2.46 LPF_A0_MSB (EEPROM Address= 0x4000002B)
          47. 8.5.1.2.47 LPF_A1 (EEPROM Address= 0x4000002C)
          48. 8.5.1.2.48 LPF_A2 (EEPROM Address= 0x4000002E)
          49. 8.5.1.2.49 .LPF_B1 (EEPROM Address= 0x40000030)
          50. 8.5.1.2.50 NORMAL_LOW (EEPROM Address= 0x40000032)
          51. 8.5.1.2.51 NORMAL_HIGH (EEPROM Address= 0x40000034)
          52. 8.5.1.2.52 LOW_CLAMP (EEPROM Address= 0x40000036)
          53. 8.5.1.2.53 HIGH_CLAMP (EEPROM Address= 0x40000038)
          54. 8.5.1.2.54 DIAG_BIT_EN (EEPROM Address= 0x4000003A)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 0-5V Voltage Output
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Data
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

PGA302-Q1 PW Package
16-Pin TSSOP
(Top View)
PGA302 PGA302-Q1_PW_TSSOP_pin_package_SLDS241.gif

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
1 VINTN I External temperature sensor - negative input
2 VINTP I External temperature sensor - positive input
3 VINPP I Resistive sensor - positive input
4 VBRGN O Bridge drive negative
5 VINPN I Resistive sensor - negative input
6 VBRGP O Bridge drive positive
7 DACCAP I/O DAC LPF capacitor
8 TEST1 O Test pin 1
9 VOUT O Analog voltage output (from DAC gain amplifier)
10 VDD P Power supply voltage
11 NC - No connect
12 TEST2 O Test pin 2
13 SDA I/O I2C interface serial data pin
14 SCL I I2C interface serial clock pin
15 GND P Ground
16 DVDD P Digital logic regulator capacitor