SLDS216 December   2017 PGA302

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Overvoltage and Reverse Voltage Protection
    6. 7.6  Linear Regulators
    7. 7.7  Internal Reference
    8. 7.8  Internal Oscillator
    9. 7.9  Bridge Sensor Supply
    10. 7.10 Temperature Sensor Supply
    11. 7.11 Bridge Offset Cancel
    12. 7.12 P Gain and T Gain Input Amplifiers (Chopper Stabilized)
    13. 7.13 Analog-to-Digital Converter
    14. 7.14 Internal Temperature Sensor
    15. 7.15 Bridge Current Measurement
    16. 7.16 One Wire Interface
    17. 7.17 DAC Output
    18. 7.18 DAC Gain for DAC Output
    19. 7.19 Non-Volatile Memory
    20. 7.20 Diagnostics - PGA30x
    21. 7.21 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Overvoltage and Reverse Voltage Protection
      2. 8.3.2  Linear Regulators
      3. 8.3.3  Internal Reference
      4. 8.3.4  Internal Oscillator
      5. 8.3.5  VBRGP and VBRGN Supply for Resistive Bridge
      6. 8.3.6  ITEMP Supply for Temperature Sensor
      7. 8.3.7  P Gain
      8. 8.3.8  T Gain
      9. 8.3.9  Bridge Offset Cancel
      10. 8.3.10 Analog-to-Digital Converter
        1. 8.3.10.1 Sigma Delta Modulator for ADC
        2. 8.3.10.2 Decimation Filter for ADC
        3. 8.3.10.3 Internal Temperature Sensor ADC Conversion
        4. 8.3.10.4 ADC Scan Mode
          1. 8.3.10.4.1 P-T Multiplexer Timing in Auto Scan Mode
      11. 8.3.11 Internal Temperature Sensor
      12. 8.3.12 Bridge Current Measurement
      13. 8.3.13 Digital Interface
      14. 8.3.14 OWI
        1. 8.3.14.1 Overview of OWI Interface
        2. 8.3.14.2 Activating and Deactivating the OWI Interface
          1. 8.3.14.2.1 Activating OWI Communication
          2. 8.3.14.2.2 Deactivating OWI Communication
        3. 8.3.14.3 OWI Protocol
          1. 8.3.14.3.1 OWI Frame Structure
            1. 8.3.14.3.1.1 Standard field structure:
            2. 8.3.14.3.1.2 Frame Structure
            3. 8.3.14.3.1.3 Sync Field
            4. 8.3.14.3.1.4 Command Field
            5. 8.3.14.3.1.5 Data Field(s)
          2. 8.3.14.3.2 OWI Commands
            1. 8.3.14.3.2.1 OWI Write Command
            2. 8.3.14.3.2.2 OWI Read Initialization Command
            3. 8.3.14.3.2.3 OWI Read Response Command
            4. 8.3.14.3.2.4 OWI Burst Write Command (EEPROM Cache Access)
            5. 8.3.14.3.2.5 OWI Burst Read Command (EEPROM Cache Access)
          3. 8.3.14.3.3 OWI Operations
            1. 8.3.14.3.3.1 Write Operation
            2. 8.3.14.3.3.2 Read Operation
            3. 8.3.14.3.3.3 EEPROM Burst Write
            4. 8.3.14.3.3.4 EEPROM Burst Read
        4. 8.3.14.4 OWI Communication Error Status
      15. 8.3.15 I2C Interface
        1. 8.3.15.1 Overview of I2C Interface
        2. 8.3.15.2 I2C Interface Protocol
        3. 8.3.15.3 Clocking Details of I2C Interface
      16. 8.3.16 DAC Output
      17. 8.3.17 DAC Gain for DAC Output
        1. 8.3.17.1 Connecting DAC Output to DAC GAIN Input
      18. 8.3.18 Memory
        1. 8.3.18.1 EEPROM Memory
          1. 8.3.18.1.1 EEPROM Cache
          2. 8.3.18.1.2 EEPROM Programming Procedure
          3. 8.3.18.1.3 EEPROM Programming Current
          4. 8.3.18.1.4 CRC
      19. 8.3.19 Diagnostics
        1. 8.3.19.1 Power Supply Diagnostics
        2. 8.3.19.2 Sensor Connectivity/Gain Input Faults
        3. 8.3.19.3 Gain Output Diagnostics
        4. 8.3.19.4 PGA302 Harness Open Wire Diagnostics
        5. 8.3.19.5 EEPROM CRC and TRIM Error
      20. 8.3.20 Digital Compensation and Filter
        1. 8.3.20.1 Digital Gain and Offset
        2. 8.3.20.2 TC and NL Correction
        3. 8.3.20.3 Clamping
        4. 8.3.20.4 Filter
      21. 8.3.21 Revision ID
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
      1. 8.5.1 Programmer's Model
        1. 8.5.1.1 Memory Map
        2. 8.5.1.2 Control and Status Registers
          1. 8.5.1.2.1  MICRO_INTERFACE_CONTROL (DI Page Address = 0x0) (DI Page Offset = 0x0C)
          2. 8.5.1.2.2  PSMON1 (M0 Address= 0x40000558) (DI Page Address = 0x2) (DI Page Offset = 0x58)
          3. 8.5.1.2.3  AFEDIAG (M0 Address= 0x4000055A) (DI Page Address = 0x2) (DI Page Offset = 0x5A)
          4. 8.5.1.2.4  P_GAIN_SELECT (DI Page Address = 0x2) (DI Page Offset = 0x47)
          5. 8.5.1.2.5  T_GAIN_SELECT (DI Page Address = 0x2) (DI Page Offset = 0x48)
          6. 8.5.1.2.6  TEMP_CTRL (DI Page Address = 0x2) (DI Page Offset = 0x4C)
          7. 8.5.1.2.7  OFFSET_CANCEL (DI Page Address = 0x2) (DI Page Offset = 0x4E)
          8. 8.5.1.2.8  PADC_DATA1 (DI Page Address = 0x0) (DI Page Offset = 0x10)
          9. 8.5.1.2.9  PADC_DATA2 (DI Page Address = 0x0) (DI Page Offset = 0x11)
          10. 8.5.1.2.10 TADC_DATA1 (DI Page Address = 0x0) (DI Page Offset = 0x14)
          11. 8.5.1.2.11 TADC_DATA2 (DI Page Address = 0x0) (DI Page Offset = 0x15)
          12. 8.5.1.2.12 DAC_REG0_1 (DI Page Address = 0x2) (DI Page Offset = 0x30)
          13. 8.5.1.2.13 DAC_REG0_2 (DI Page Address = 0x2) (DI Page Offset = 0x31)
          14. 8.5.1.2.14 OP_STAGE_CTRL (DI Page Address = 0x2) (DI Page Offset = 0x3B)
          15. 8.5.1.2.15 EEPROM_ARRAY (DI Page Address = 0x5) (DI Page Offset = 0x00 - 0x7F)
          16. 8.5.1.2.16 EEPROM_CACHE_BYTE0 (DI Page Address = 0x5) (DI Page Offset = 0x80)
          17. 8.5.1.2.17 EEPROM_CACHE_BYTE1 (DI Page Address = 0x5) (DI Page Offset = 0x81)
          18. 8.5.1.2.18 EEPROM_PAGE_ADDRESS (DI Page Address = 0x5) (DI Page Offset = 0x82)
          19. 8.5.1.2.19 EEPROM_CTRL (DI Page Address = 0x5) (DI Page Offset = 0x83)
          20. 8.5.1.2.20 EEPROM_CRC (DI Page Address = 0x5) (DI Page Offset = 0x84)
          21. 8.5.1.2.21 EEPROM_STATUS (DI Page Address = 0x5) (DI Page Offset = 0x85)
          22. 8.5.1.2.22 EEPROM_CRC_STATUS (DI Page Address = 0x5) (DI Page Offset = 0x86)
          23. 8.5.1.2.23 EEPROM_CRC_VALUE (DI Page Address = 0x5) (DI Page Offset = 0x87)
          24. 8.5.1.2.24 H0 (EEPROM Address= 0x40000000)
          25. 8.5.1.2.25 H1 (EEPROM Address= 0x40000002)
          26. 8.5.1.2.26 H2 (EEPROM Address= 0x40000004)
          27. 8.5.1.2.27 H3 (EEPROM Address= 0x40000006)
          28. 8.5.1.2.28 G0 (EEPROM Address= 0x40000008)
          29. 8.5.1.2.29 G1 (EEPROM Address= 0x4000000A)
          30. 8.5.1.2.30 G2 (EEPROM Address= 0x4000000C)
          31. 8.5.1.2.31 G3 (EEPROM Address= 0x4000000E)
          32. 8.5.1.2.32 N0 (EEPROM Address= 0x40000010)
          33. 8.5.1.2.33 N1 (EEPROM Address= 0x40000012)
          34. 8.5.1.2.34 N2 (EEPROM Address= 0x40000014)
          35. 8.5.1.2.35 N3 (EEPROM Address= 0x40000016)
          36. 8.5.1.2.36 M0 (EEPROM Address= 0x40000018)
          37. 8.5.1.2.37 M1 (EEPROM Address= 0x4000001A)
          38. 8.5.1.2.38 M2 (EEPROM Address= 0x4000001C)
          39. 8.5.1.2.39 M3 (EEPROM Address= 0x4000001E)
          40. 8.5.1.2.40 PADC_GAIN (EEPROM Address= 0x40000020)
          41. 8.5.1.2.41 TADC_GAIN (EEPROM Address= 0x40000021)
          42. 8.5.1.2.42 PADC_OFFSET (EEPROM Address= 0x40000022)
          43. 8.5.1.2.43 TADC_OFFSET (EEPROM Address= 0x40000024)
          44. 8.5.1.2.44 TEMP_SW_CTRL (EEPROM Address= 0x40000028)
          45. 8.5.1.2.45 DAC_FAULT_MSB (EEPROM Address= 0x4000002A)
          46. 8.5.1.2.46 LPF_A0_MSB (EEPROM Address= 0x4000002B)
          47. 8.5.1.2.47 LPF_A1 (EEPROM Address= 0x4000002C)
          48. 8.5.1.2.48 LPF_A2 (EEPROM Address= 0x4000002E)
          49. 8.5.1.2.49 .LPF_B1 (EEPROM Address= 0x40000030)
          50. 8.5.1.2.50 NORMAL_LOW (EEPROM Address= 0x40000032)
          51. 8.5.1.2.51 NORMAL_HIGH (EEPROM Address= 0x40000034)
          52. 8.5.1.2.52 LOW_CLAMP (EEPROM Address= 0x40000036)
          53. 8.5.1.2.53 HIGH_CLAMP (EEPROM Address= 0x40000038)
          54. 8.5.1.2.54 DIAG_BIT_EN (EEPROM Address= 0x4000003A)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 0-5V Voltage Output
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Data
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
VDD VDD voltage –20 20 V
VOUT VOUT voltage –20 20 V
Voltage at VP_OTP –0.3 8 V
Voltage at sensor input and drive pins –0.3 5 V
Voltage at any IO pin –0.3 2 V
IDD, Short on VOUT Supply current 25 mA
TJmax Maximum junction temperature 155 °C
Tlead Lead temperature (soldering, 10 s) 260 °C
Tstg Storage temperature –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions are not implied. Exposure to Absolute-Maximum-Rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins except 9 and 10 ±2000 V
Pins 9 and 10 ±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) All pins except 1, 8, 9, and 16 ±500
Pins 1, 8, 9, and 16 ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Power supply voltage 4.5 5 5.5(1) V
Slew Rate VDD = 0 to 5 V; decoupling capacitor on VDD = 10 nF 5 V/ns
IDD Power supply current - Normal Operation No load on VBRG, No load on DAC 6.5 10 mA
TA Operating ambient temperature –40 150 °C
Programming temperature EEPROM –40 140 °C
Start-up time (including analog and digital) VDD ramp rate 1 V/µs 250 µs
Capacitor on VDD Pin Not including series resistance 100 nF
(1) The analog circuits in the device will be shut off for VDD>OVP. However, digital logic inside the device will continue to operate. The device will withstand VDD<VDD_ABSMAX without damage

7.4 Thermal Information

THERMAL METRIC(1) PGA302 UNIT
PW (TSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 96.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 27.3 °C/W
RθJB Junction-to-board thermal resistance 43.3 °C/W
ψJT Junction-to-top characterization parameter 1.2 °C/W
ψJB Junction-to-board characterization parameter 42.7 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

7.5 Overvoltage and Reverse Voltage Protection

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reverse voltage –20 V
Overvoltage analog shutdown –40°C to 150°C 5.65 V

7.6 Linear Regulators

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDVDD DVDD voltage - operating Capacitor on DVDD pin = 100 nF 1.76 1.8 1.86 V
VDVDD_POR DVDD voltage - digital POR 1.4 1.6 1.75 V
DVDD voltage - digital POR Hysteresis 0.1 V
VVDD_POR VDD voltage - digital POR 4 V
VDD voltage - digital POR Hysteresis 0.1 V

7.7 Internal Reference

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference voltage (including reference buffer) 2.5 V
Reference initial error –0.5% 0.5%
Reference voltage TC –250 250 ppm/°C
PSRR VDD Ripple Conditions:
  • VDD DC Level = 5 V
  • VDD Ripple Amplitude = 100 mV
  • VDD Ripple Frequency Range: 30 Hz to 50 KHz
  • Calculate PSRR using the formula:
    20log10(Amplitude of Reference
    Voltage/Amplitude of VDD ripple)
 –35 dB

7.8 Internal Oscillator

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL OSCILLATOR
Internal oscillator frequency TA = 25°C 8 MHz
Internal oscillator frequency variation Across operating temperature –3% 3%

7.9 Bridge Sensor Supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBRG SUPPLY FOR RESISTIVE BRIDGE SENSORS
VBRGP-VBRGN Bridge supply voltage ILOAD = 0 to 8.5mA 2.4 2.5 2.6 V
PMISMATCH Mismatch between bridge supply voltage, temperature variation, and ADC reference temperature variation Procedure to calculate drift mismatch:
  1. VDD = 5 V
  2. Connect 5-KΩ, Zero TC bridge with 5mV output to device
  3. Set P GAIN = 200V/V
  4. Set Temperature = 25°C,
    Measure ADC Code by
    averaging 512 samples
  5. Set Temperature = –40°C,
    Measure ADC Code by
    averaging 512 samples
  6. Set Temperature = 125°C,
    Measure ADC Code by
    averaging 512 samples
  7. Calculate Drift using the formula: (ADC Code at Temperature – ADC Code at 25°C)/((ADC Code at 25°C)×(Temperature – 25))
 –250 +250 ppm/°C
IBRG Current Supply to the Bridge 8.5 mA
Bridge short-circuit current limit TA = 25°C;
VVDD= 5 V		 9 25 mA
CBRG Capacitive Load RBRG = 5 kΩ 2 nF

7.10 Temperature Sensor Supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ITEMP SUPPLY FOR TEMPERATURE SENSOR(1)
ITEMP Current supply to temperature sensor Control bit = 0b000 45 50 55 µA
Control bit = 0b001 90 100 110
Control bit = 0b010 180 200 220
Control bit = 0b011 850 1000 1150
Control bit = 0b1xx OFF
TMISMATCH Mismatch between ITEMP temperature variation and ADC reference temperature variation Procedure to calculate drift mismatch:
  1. VDD = 5 V
  2. Connect 1-KΩ, Zero TC resistor to the temperature input pins of device
  3. Set T GAIN = 1.33 V/V
  4. Set ITEMP = 100 µA
  5. Set Temperature = 25°C, Measure ADC Code by averaging 512 samples
  6. Set Temperature = -40°C, Measure ADC Code by averaging 512 samples
  7. Set Temperature = 125°C, Measure ADC Code by averaging 512 samples
  8. Calculate Drift using the formula: (ADC Code at Temperature – ADC Code at 25°C)/((ADC Code at 25°C)×(Temperature – 25))
 –250 +250 ppm/°C
ZOUT Output Impedance Ensured by design 15 MΩ
CTEMP Capacitive load 100 nF
(1) Not applicable for 8-pin package options
PGA302 vbrgRatio_pga902_lds203.gif Figure 1. Bridge Supply and ADC Reference are Ratiometric

7.11 Bridge Offset Cancel

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Offset cancel range –54.75 +54.75 mV
Offset cancel tolerance –10% +10%
Offset cancel resolution (4 bits) 10 mV

7.12 P Gain and T Gain Input Amplifiers (Chopper Stabilized)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Gain steps (3 bits) 000, at DC 1.31 1.33 1.35 V/V
001 1.97 2 2.03
010 3.92 4 4.08
011 9.6 10 10.4
100 19 20 21
101 38 40 42
110 96 100 104
111 185 200 215
Bandwidth PGAIN = 1.33 680 kHz
PGAIN = 2 470
PGAIN = 4 250
PGAIN = 10 104
PGAIN = 20 80
PGAIN = 40 72
PGAIN = 100 30
PGAIN = 200 15
Input offset voltage 14 µV
Gain temperature drift Gain = 200 V/V –250 +250 ppm/°C
Input bias current 5 nA
Common-mode voltage range Depends on Selected Gain, Bridge Supply and Sensor Span (1) V
Common-mode rejection ratio FCM = 50 Hz; ensured by design 110 dB
Input impedance Ensured by design 10 MΩ
(1) Common Mode at P Gain Input and Output:
  1. The single-ended voltage of positive/negative pin at the Gain input should be between +0.02 V and +4.38 V

7.13 Analog-to-Digital Converter

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Sigma delta modulator frequency 4 MHz
ADC voltage input range –2.5 2.5 V
Number of bits 16 bits
ADC 2's complement code for –2.5-V differential input 2's Complement 8000hex LSB
ADC 2's complement code for 0-V differential input 0000hex LSB
ADC 2's complement code for 2.5-V differential input 7FFFhex LSB
Output sample period (no latency) Sample period control bit = 0b00 96 µs
ADC multiplexer switching time 1 µs
Effective number of bits (ENOB) Procedure to calculate ENOB:
  1. VDD = 5 V
  2. Temperature = –40°C, 25°C, 125°C, 150°C
  3. Connect 5-KΩ, Zero TC bridge to the pressure input pins device with near zero differential voltage
  4. Set P GAIN = 200 V/V
  5. Set ADC sample period to 96 µS
  6. Set input MUX to pressure channel
  7. Measure ADC
  8. Calculate ENOB using the formula: 20log10((32768/2/√2)/(ADC code
    rms))/6.02
 11.4 bits
ENOB in the presence of crosstalk between P and T channels Procedure to calculate ENOB in the presence of crosstalk:
  1. VDD = 5 V
  2. Temperature = –40°C, 25°C, 125°C, 150°C
  3. Connect 5-KΩ, Zero TC bridge to the pressure input pins device
  4. Set P GAIN = 200 V/V
  5. Set ADC sample period to 96 µS
  6. Connect 1-KHz, 1.25-V common mode, 1-Vpp sine wave through 100-Ω source impedance to temperature input pins device
  7. Set T GAIN = 1.33 V/V
  8. Set input MUX to pressure channel
  9. Measure ADC
  10. Calculate ENOB using the formula: 20log10((32768/2/√2)/(ADC code
    rms))/6.02
 11.4 bits
Linearity Procedure to calculate Linearity:
  1. VDD = 5 V
  2. Temperature = 25°C
  3. Connect 5-KΩ, Zero TC bridge to the pressure input pins of the device with 30%FS to 70%FS input voltages
  4. Set GAIN = 200 V/V
  5. Set ADC sample period to 96 µS
  6. Set input MUX to pressure channel
  7. Measure P ADC
  8. Calculate linearity as maximum deviation obtaining using end-point fit
 ±0.8 %FS

7.14 Internal Temperature Sensor

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal temperature sensor range –40 150 °C
Gain (1) 16-bit ADC 20 LSB/°C
Offset 5700 LSB
Total error after calibration using typical gain and offset values(2) ±6 °C
(1) ADC = Gain × Temperature + offset
(2) TI does not calibrate the sensor. User has to the calibrate the internal temperature sensor on their production line.

7.15 Bridge Current Measurement

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Bridge current range 0 8500 µA
Gain if T GAIN is configured for 1.33 Gain 2250 LSB/mA
Offset T GAIN is configured for 1.33 Gain 2075 LSB
Total temperature drift Procedure to calculate Total Temperature Drift:
  1. VDD = 5 V
  2. Temperature = –40°C, 25°C, 125°C,
    150°C
  3. Connect 5-KΩ, Zero TC bridge to the pressure input pins device with near zero differential voltage
  4. Set T GAIN = 1.33 V/V
  5. Set input MUX to bridge current
  6. Measure T ADC
  7. Filter ADC code using 10-Hz 1st order filter
  8. Calculate Total Temperature Drift using the formula: (ADC code at
    Temperature – ADC code at
    25°C)/(Temperature – 25°C)/(ADC code
    at 25°C) × 1e6
 600 ppm/°C

7.16 One Wire Interface

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Communication baud rate 2400 9600 bits per
second
OWI_ENH OWI activation high OWI_ENL V
OWI_ENL OWI activation low 6.8 V
OWI_LOW Activation signal pulse low time OWI_DGL_CNT_SEL = 0 1 ms
OWI_DGL_CNT_SEL = 1 10
OWI_HIGH Activation signal pulse high time OWI_DGL_CNT_SEL = 0 1 ms
OWI_DGL_CNT_SEL = 1 10
OWI_VIH OWI transceiver Rx threshold for high 5.3 V
OWI_VIL OWI transceiver Rx threshold for low 4.7 V
OWI_IOH OWI transceiver Tx threshold for hIgh 900 1300 µA
OWI_IOL OWI transceiver Tx threshold for low 2 5 µA

7.17 DAC Output

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DAC Reference Voltage Ratiometric Reference 0.25 × Vddp V
DAC Resolution 14 Bits

7.18 DAC Gain for DAC Output

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Buffer gain (see Figure 2) 3.9 4 4.3 V/V
Gain bandwidth product No Load, No DACCAP, Nominal Gain 1 MHz
Offset error (includes DAC errors) Calculate Gain Nonlinearity at VDD = 5 V and 25°C as follows:
  1. Apply DAC Code = 819d at 25°C and
    0-mA load and measure voltage at VOUT
  2. Apply DAC Code = 8192d at 25°C and
    0-mA load and measure voltage at VOUT
  3. Apply DAC Code = 15564d at 25°C and
    0-mA load and measure voltage at VOUT
  4. Linear Curve-fit the three measurements using end-point method and determine offset
 ±20 mV
Gain nonliearity (includes DAC errors) Calculate Gain Nonlinearity at VDD = 5 V and 25°C as follows:
  1. Apply DAC Code = 819d at 25°C and
    0-mA load and measure voltage at VOUT
  2. Apply DAC Code = 8192d at 25°C and
    0-mA load and measure voltage at VOUT
  3. Apply DAC Code = 15564d at 25°C and
    0-mA load and measure voltage at VOUT
  4. Linear Curve-fit the three measurements using end-point method and determine nonlinearity
 ±600 µV
Total unadjusted error Calculate Gain Nonlinearity at VDD = 5 V and 25°C as follows:
  1. Apply DAC Code = 819d at 25°C and
    0-mA load and measure voltage at VOUT
  2. Apply DAC Code = 8192d at 25°C and
    0-mA load and measure voltage at VOUT
  3. Apply DAC Code = 15564d at 25°C and
    0-mA load and measure voltage at VOUT
  4. Linear Curve-fit the three measurements using end-point method and determine total unadjusted error by comparing values against ideal line. Error is w.r.t. 4V FS.
 –2 2 %FSO
Ratiometric error due to change in temperature and load current for DAC code = 819d to 15564d. Calculate ratiometric error at VDD = 5 V and at DAC codes as follows:
  1. Apply DAC Code at 25°C and 0-mA load, and measure voltage at VOUT
  2. Change temperature between –40°C to 150°C, and measure voltage at VOUT
  3. Change load current between 0 mA to
    2.5 mA, and measure voltage at VOUT
  4. Ratiometric Error = ((VOUT at
    TEMPERATURE at LOAD) – (VOUT at
    25°C at 0 mA))
 –10 10 mV
Ratiometric error due to change in VDD for DAC code = 819d to 15564d. Calculate ratiometric error at DAC codes as follows:
  1. Apply DAC Code at 25°C and 0-mA load, and measure voltage at VOUT
  2. Change VDD between 4.5 V and 5.5 V, and measure voltage at VOUT
  3. Change temperature between –40°C to 150°C, and measure voltage at VOUT
  4. Ratiometric Error = ((VOUT at VDD, T) – (VOUT at 5 V, 25°C) × VDD/5 V)
 –12 12 mV
Settling time (first order response) DAC Code 819d to 15564d step and CLOAD = 100 nF. Output is 99% of Final Value 100 µs
Zero code voltage DAC code = 0000h,
IDAC = 1 mA		 100(1) mV
DAC code = 0000h,
IDAC = 2.5 mA		 250 mV
Full code voltage Output when DAC code is 3FFFh,
IDAC = –1 mA		 Vddp – 0.15(1) V
Output when DAC code is 3FFFh,
IDAC = –2.5 mA		 Vddp – 0.28 V
Output current DAC Code = 3FFFh , DAC Code = 0000h ±2.5 mA
Short circuit source current DAC code = 3FFFh 10 40 mA
Short circuit sink current DAC code = 0000h 10 40 mA
Output voltage noise (GAIN = 4X) ƒ = 10 Hz to 1 KHz, VDD = 4.5 V, DAC code = 1FFFh, no capacitor on DACCAP pin, temperature = 25°C 80 µVpp
Pullup resistance 2 47 KΩ
Pulldown resistance 2 47 KΩ
Capacitance 0.1 1000 nF
(1) See Figure for voltage output bands.
PGA302 output1_lds203.gif Figure 2. PGA302 Output Buffer

7.19 Non-Volatile Memory

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EEPROM Size 128 Bytes
Erase/write cycles 1000 Cycles
Programming time 1 2-byte page 8 ms
Data retention 10 Years

7.20 Diagnostics - PGA30x

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBRG_OV Resistive bridge sensor supply overvoltage threshold 7.5% VBRG
VBRG_UV Resistive bridge sensor supply undervoltage threshold –4% VBRG
VDD_OV VDD OV threshold 5.51 V
DVDD_OV DVDD OV threshold 1.85 V
REF_OV Reference overvoltage threshold 2.69 V
REF_UV Reference undervoltage threshold 2.42 V
P_DIAG_PD Gain input diagnostics pulldown resistor value VINPP and VINPN each has pulldown resistor 1 MΩ
2
3
4
T_DIAG_PD T gain input diagnostics pulldown resistor value VINTP and VINTN each has pulldown resistor 1 MΩ
VINP_OV P gain input overvotlage threshold value VINPP and VINPN each has threshold comparator 90% VBRDG
84%
78%
70%
VINP_UV P gain input undervotlage threshold value VINPP and VINPN each has threshold comparator 10% VBRDG
16%
24%
30%
VINT_OV T gain input overvoltage VINTP and VINTN 90% VBRG
VINT_UV T gain input undervotlage 10% VBRG
PGAIN_OV P gain output overvoltage 2.5 V
PGAIN_UV P gain output undervoltage 0.95 V
TGAIN_OV T gain output overvoltage 2.5 V
TGAIN_UV T gain output undervoltage 0.67 V
HARNESS FAULT1 Open wire VOUT voltage - open VDD with pullup on VOUT Pullup resistor is 2 KΩ to 47 KΩ ±5%. across temperature 5% VDD
HARNESS_
FAULT2		 Open wire VOUT voltage - open GND with pulldown on VOUT Pulldown resistor is 2 KΩ to 47 KΩ ±5%, across temperature 95% VDD

7.21 Typical Characteristics

PGA302 D001-tc-internal-temperature-sensor-slds239.gif Figure 3. Internal Temperature Sensor
PGA302 D003-tc-afe-and-adc-linearity-error-slds239.gif Figure 5. AFE and ADC Linearity Error
PGA302 D005-tc-ratiometric-error-v-vdd-supply-slds239.gif Figure 7. Ratiometric Error vs VDD Supply
PGA302 D002-tc-ade-and-adc-linearity-error-slds239.gif Figure 4. ADE and ADC Linearity Error
PGA302 D004-tc-dac-linearity-error-slds239.gif Figure 6. DAC Linearity Error
PGA302 D006-tc-afe-gain-v-common-mode-input-slds239.gif Figure 8. AFE Gain vs Common-Mode Input