SLPS755A October   2023  – December 2023 RES11A-Q1

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 AEC-Q200 Qualification Testing
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 DC Measurement Configurations
    2. 6.2 AC Measurement Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Ratiometric Matching
      2. 7.3.2 Ratiometric Drift
      3. 7.3.3 Predictable Voltage Coefficient
      4. 7.3.4 Ultra-Low Noise
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Discrete Difference Amplifier
        1. 8.1.1.1 Difference-Amplifier Common-Mode Rejection Analysis
      2. 8.1.2 Discrete Instrumentation Amplifiers
        1. 8.1.2.1 Instrumentation Amplifier Common-Mode Rejection Analysis
      3. 8.1.3 Fully Differential Amplifier
    2. 8.2 Typical Application
      1. 8.2.1 Common-Mode Shifting Input Stage
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 9.1.1.3 TI Reference Designs
        4. 9.1.1.4 Filter Design Tool
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDF|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 DC Measurement Configurations

An example of the circuit configuration used for dc measurements is shown in Figure 6-1. Voltage VDx refers to the voltage across a given divider, such as VD1 for divider 1. Voltage VRx refers to the voltage across a given resistor, such as VRIN1 for RIN1 or VRG1 for RG1.

GUID-20231215-SS0I-X5RW-Z0NQ-GTXNGVB2TFKM-low.svg Figure 6-1 DC Measurement Terminology for Divider 1

When the RES11A-Q1 is used to set the gain of an op amp (shown in Figure 6-2), the ratio of the resistors in a divider sets the amplifier gain according to G = RG / RIN. Discrete-difference-amplifier and instrumentation-amplifier circuits are variations on this ratiometric use case. Typical and maximum parameter values for ratio tolerance (tD1, tD2) are expressed in terms of RGx / RINx to simplify calculations for these circuits.

However, another valid use case of the RES11A-Q1 is a simple voltage divider, where the midpoint voltage VMID is equal to the input voltage VD multiplied by RG / (RIN + RG), or by RIN / (RIN + RG) as shown in Figure 6-3. Typical and maximum parameter values for ratio tolerance of these voltage-divider circuits, expressed in terms of RINx / (RINx + RGx), are provided.

GUID-20231206-SS0I-N6LK-WZ3T-7CPKGLKWMDZT-low.svgFigure 6-2 Amplifier Gain Circuit
GUID-20231206-SS0I-HJZ4-4BLV-4BSJ179RPGKR-low.svgFigure 6-3 Voltage-divider circuit

Figure 6-4 shows the circuit configuration used for CMRR calculations. For an ideal amplifier with no offset and infinite CMRR, the effective circuit CMRR is entirely a function of the matching of the resistors. See Section 8.1.1.1 and the Optimizing CMRR in Differential Amplifier Circuits With Precision Matched Resistor Divider Pairs application note for more information.

GUID-20231201-SS0I-S9GS-W7MN-FHGRHLSFQ5WM-low.svg Figure 6-4 CMRR Calculation Reference Schematic