SLLSEW9A December 2016 – June 2018 SN65DSI84-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | EVEN_ODD_SWAP | CHA_REVERSE_LVDS | CHB_REVERSE_LVDS | Reserved | CHA_LVDS_TERM | CHB_LVDS_TERM | |
R | R/W | R/W | R/W | R | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Reserved | R | Reserved | |
6 | EVEN_ODD_SWAP | R/W | 0 | 0 – Odd pixels routed to LVDS Channel A and Even pixels routed to LVDS Channel B (default)
1 – Odd pixels routed to LVDS Channel B and Even pixels routed to LVDS Channel A Note: When the SN65DSI84-Q1 is in two stream mode (CSR 0x10.6:5 = ‘10’), setting this bit to ‘1’ will cause the video stream from DSI Channel A to be routed to LVDS Channel B and the video stream from DSI Channel B to be routed to LVDS Channel A. |
5 | CHA_REVERSE_LVDS | R/W | 0 | This bit controls the order of the LVDS pins for Channel A.
0 – Normal LVDS Channel A pin order. LVDS Channel A pin order is the same as listed in the Terminal Assignments Section. (default) 1 – Reversed LVDS Channel A pin order. LVDS Channel A pin order is remapped as follows:
|
4 | CHB_REVERSE_LVDS | R/W | 0 | This bit controls the order of the LVDS pins for Channel B.
0 – Normal LVDS Channel B pin order. LVDS Channel B pin order is the same as listed in the Terminal Assignments Section. (default) 1 – Reversed LVDS Channel B pin order. LVDS Channel B pin order is remapped as follows:
|
3-2 | Reserved | R | Reserved | |
1 | CHA_LVDS_TERM | R/W | 1 | This bit controls the near end differential termination for LVDS Channel A. This bit also affects the output voltage for LVDS Channel A.
0 – 100Ω differential termination 1 – 200Ω differential termination (default) |
0 | CHB_LVDS_TERM | R/W | 1 | This bit controls the near end differential termination for LVDS Channel B. This bit also affects the output voltage for LVDS Channel B.
0 – 100Ω differential termination 1 – 200Ω differential termination (default) |