SLLS666F September   2005  – March 2023 SN65HVD50 , SN65HVD52 , SN65HVD53 , SN65HVD54 , SN65HVD55

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Available Options
  6. 6 Pin Configurations
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Electrostatic Discharge Protection
    4. 7.4 Driver Electrical Characteristics
    5. 7.5 Driver Switching Characteristics
    6. 7.6 Receiver Electrical Characteristics
    7. 7.7 Receiver Switching Characteristics
    8. 7.8 Thermal Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Device Information
    1. 9.1 Ll-Power Standby Mode
    2. 9.2 Function Tables
    3. 9.3 Equivalent Input and Output Schematic Diagrams
  10. 10Application and Implementation
    1. 10.1 Thermal Characteristics of IC Packages
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1 Ll-Power Standby Mode

When both the driver and receiver are disabled (DE low and RE high) the device is in standby mode. If the enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active.

GUID-68025AD1-4508-40CF-9D1D-E006BBA31A5D-low.gifFigure 9-1 Low-Power Standby Logic Diagram

If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after the enable times given by tPZH2 and tPZL2 in the driver switching characteristics. If the D input is open when the driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature.

If only the receiver is re-enabled ( RE transitions to low) the receiver output is driven according to the state of the bus inputs (A and B) after the enable times given by tPZH2 and tPZL2 in the receiver switching characteristics. If there is no valid state on the bus the receiver responds as described in the failsafe operation section.

If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver outputs are valid.