SCLS249L October   1995  – October 2023 SN54AHC86 , SN74AHC86

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Switching Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Noise Characteristics
    8. 6.8 Operating Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Power Considerations
        1. 9.2.1.1 Input Considerations
        2. 9.2.1.2 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support (Analog)
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • RGY|14
  • DB|14
  • DGV|14
  • PW|14
  • BQA|14
  • N|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2 Detailed Design Procedure

  1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout section.
  2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; it will, however, ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the SN74AHC1G04-Q1 to one or more of the receiving devices.
  3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω, so that the maximum output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load measured in MΩ; much larger than the minimum calculated previously.
  4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however, can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation.