SCES677E September   2006  – December 2022 SN74LVC1T45-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics: VCCA = 1.8 V ±0.15 V
    7. 6.7  Switching Characteristics: VCCA = 2.5 V ±0.2 V
    8. 6.8  Switching Characteristics: VCCA = 3.3 V ±0.3 V
    9. 6.9  Switching Characteristics: VCCA = 5 V ±0.5 V
    10. 6.10 Typical Characteristics
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1.      Application and Implementation
        1. 8.1 Application Information
          1. 8.1.1 Enable Times
        2. 8.2 Typical Applications
          1. 8.2.1 Unidirectional Logic Level-Shifting Application
            1. 8.2.1.1 Design Requirements
            2. 8.2.1.2 Detailed Design Procedure
            3. 8.2.1.3 Application Curves
          2. 8.2.2 Bidirectional Logic Level-Shifting Application
            1. 8.2.2.1 Detailed Design Procedure
            2. 8.2.2.2 Application Curves
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.1 Detailed Design Procedure

Table 8-2 shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1.

Table 8-2 Data Transmission
STATEDIR CTRLI/O-1I/O-2DESCRIPTION
1HOutInSYSTEM-1 data to SYSTEM-2
2HHi-ZHi-ZSYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on pullup or pulldown.(1)
3LHi-ZHi-ZDIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or pulldown.(1)
4LOutInSYSTEM-2 data to SYSTEM-1
(1) SYSTEM-1 and SYSTEM-2 must use the same conditions, that is, both pullup or both pulldown.