SLASF29 January   2022 TAA5242

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 6.7 Switching Characteristics: TDM, I2S or LJ Interface
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Audio Serial Interfaces
        1. 8.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 8.3.2.2 Inter IC Sound (I2S) Interface
      3. 8.3.3 Analog Input Configurations
      4. 8.3.4 Reference Voltage
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
  11. 10Power Supply Recommendations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20231211-SS0I-NHX3-PSNM-Z9QQ6SJTGVL4-low.svg Figure 5-1 28-Pin QFN With Exposed Thermal Pad, Top View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
VSS A1 Ground Short directly to board Ground Plane.
DREG 1 Digital Supply Digital on-chip regulator output voltage for digital supply (1.5 V, nominal)
BCLK 2 Digital I/O Audio serial data interface bus bit clock
FSYNC 3 Digital I/O Audio serial data interface bus frame synchronization signal
DOUT 4 Digital Output Audio serial data interface bus output
MD6 5 Digital Input TDM Mode: MD6= DAISY_DIN
I2S/LJ Mode: MD6=0: Stereo ADC Enabled; MD6=1: Mono Channel 1
IOVDD 6 Digital Supply Digital I/O power supply (1.8 V or 3.3 V, nominal)
VSS A2 Ground Short directly to board Ground Plane.
MD1 7 Digital Input Controller Mode: Frame Rate and BCLK frequency selection
Target Mode: AVDD Supply and Word Length selection
MD2 8 Digital Input Controller Mode: Frame Rate and BCLK frequency selection
Target Mode: AVDD Supply and Word Length selection
MD3 9 Digital Input Controller Mode: Controller Clock Input
Target Mode: Digital HPF and Data Slot selection
MD4 10 Digital Input ADC mode selection
GPO 11 Digital Output Interrupt Output
MD5 12 Digital Input ADC mode selection
VSS A3 Ground Short directly to board Ground Plane.
MD0 13 Analog Input Multi-Level Analog input for Controller/Target and I2S/TDM/LJ selection
MICBIAS 14 Analog MICBIAS Output (Porgrammable output upto 11V)
IN1P 15 Analog Input Analog Input 1P Pin
IN1M 16 Analog Input Analog Input 1M Pin
IN2P 17 Analog Input Analog Input 2P Pin
IN2M 18 Analog Input Analo Input 2M Pin
VSS A4 Ground Short directly to board Ground Plane.
OUT1M 19 Analog Output Analog Output 1M Pin
OUT1P 20 Analog Output Analog Output 1P Pin
OUT2P 21 Analog Output Analog Output 2P Pin
OUT2M 22 Analog Output Analog Output 2M Pin
AVDD 23 Analog Supply Analog power (3.3 V, nominal)
VREF 24 Analog Analog reference voltage filter output
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.