SLASF28 December   2023 TAC5142

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 6.7 Switching Characteristics: TDM, I2S or LJ Interface
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Audio Serial Interfaces
        1. 8.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 8.3.2.2 Inter IC Sound (I2S) Interface
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Analog Input Output Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 ADC Signal-Chain
        1. 8.3.6.1 Digital High-Pass Filter
        2. 8.3.6.2 Configurable Digital Decimation Filters
          1. 8.3.6.2.1 Linear Phase Filters
            1. 8.3.6.2.1.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.2.1.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.2.1.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.2.1.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.2.1.5 Sampling Rate: 96 kHz or 88.2 kHz
      7. 8.3.7 DAC Signal-Chain
        1. 8.3.7.1 Configurable Digital Interpolation Filters
          1. 8.3.7.1.1 Linear Phase Filters
            1. 8.3.7.1.1.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.7.1.1.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.7.1.1.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.7.1.1.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.7.1.1.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.7.1.1.6 Sampling Rate: 384 kHz or 352.8 kHz
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
  11. 10Power Supply Recommendations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2 Audio Serial Interfaces

Digital audio data flows between the host processor and the TAC5142 on the digital audio serial interface (ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for the I2S and LJF, and the pin-selectable controller-target configurability for bus clock lines.

The device supports an audio bus controller or target mode of operation using the hardware pin MD0. In target mode, FSYNC and BCLK work as input pins whereas in controller mode, FSYNC and BCLK work as output pins generated by the device. Table 8-1 shows the master and slave mode selection using the MD0 pin.

Table 8-1 Controller and Target Mode Selection
MD0 CONTROLLER AND TARGET SELECTION
Short to Ground Target I2S Mode
Short to Ground with 4.7K Ohms Target TDM Mode
Short to AVDD Controller I2S Mode
Short to AVDD with 4.7K Ohms Controller TDM Mode
Short to AVDD with 22K Ohms Target LJ Mode

The word length for audio serial interface (ASI) in TAC5142 can be selected through MD1 and MD2 Pins in target mode of operation. In controller mode, fixed word length of 32 bits is supported. The TAC5142 also supports 1.8V AVDD operation in target mode with 32 bit word length. Table 8-2 shows the configuration table for setting word length and AVDD supply voltage

Table 8-2 Word Length and Supply Mode Selection
MD1 MD2 CONTROLLER AND TARGET SELECTION
Low Low Word Length=32

AVDD=3.3V
Low High Word Length=32

AVDD=1.8V
High Low Word Length=24

AVDD=3.3V
High High Word Length=16

AVDD=3.3V

The TAC5142 offers slot configuration for target TDM mode of operation. This can be selected through MD3 pin when MD0 is configured in target TDM mode. For options on MD3 in other modes of operation, refer to Digital High-Pass Filter. Table 8-3 shows the slots selected in Target TDM mode of operation based on MD3 pin.

Table 8-3 TDM Slot Selection for Target Mode
MD3 ADC SLOTS DAC SLOTS
Low ADC Data on Slot 0 and 1 DAC Data on Slot 0 and 1
High ADC Data on Slot 2 and 3 DAC Data on Slot 2 and 3