SLASF32 December   2023 TAD5142

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 5.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hardware Control
      2. 7.3.2 Audio Serial Interfaces
        1. 7.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 7.3.2.2 Inter IC Sound (I2S) Interface
      3. 7.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 7.3.4 Analog Output Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 DAC Signal-Chain
        1. 7.3.6.1 Configurable Digital Interpolation Filters
          1. 7.3.6.1.1 Linear Phase Filters
            1. 7.3.6.1.1.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 7.3.6.1.1.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 7.3.6.1.1.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 7.3.6.1.1.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 7.3.6.1.1.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 7.3.6.1.1.6 Sampling Rate: 384 kHz or 352.8 kHz
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Phase-Locked Loop (PLL) and Clock Generation

The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the ADC and DAC modulators and digital filter engine, as well as other control blocks.

In target mode of operation, the device supports the various output data sample rates (of the FSYNC signal frequency) and the BCLK to FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming. Table 7-3 and Table 7-4 list the supported FSYNC and BCLK frequencies.

Table 7-3 Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies
BCLK TO FSYNC RATIO BCLK (MHz)
FSYNC
(8 kHz)		 FSYNC
(16 kHz)		 FSYNC
(24 kHz)		 FSYNC
(32 kHz)		 FSYNC
(48 kHz)		 FSYNC
(96 kHz)		 FSYNC
(192 kHz)
16 Reserved 0.256 0.384 0.512 0.768 1.536 3.072
24 Reserved 0.384 0.576 0.768 1.152 2.304 4.608
32 0.256 0.512 0.768 1.024 1.536 3.072 6.144
48 0.384 0.768 1.152 1.536 2.304 4.608 9.216
64 0.512 1.024 1.536 2.048 3.072 6.144 12.288
96 0.768 1.536 2.304 3.072 4.608 9.216 18.432
128 1.024 2.048 3.072 4.096 6.144 12.288 24.576
192 1.536 3.072 4.608 6.144 9.216 18.432 Reserved
256 2.048 4.096 6.144 8.192 12.288 24.576 Reserved
384 3.072 6.144 9.216 12.288 18.432 Reserved Reserved
512 4.096 8.192 12.288 16.384 24.576 Reserved Reserved
Table 7-4 Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies
BCLK TO FSYNC RATIO BCLK (MHz)
FSYNC
(7.35 kHz)		 FSYNC
(14.7 kHz)		 FSYNC
(22.05 kHz)		 FSYNC
(29.4 kHz)		 FSYNC
(44.1 kHz)		 FSYNC
(88.2 kHz)		 FSYNC
(176.4 kHz)
16 Reserved Reserved 0.3528 0.4704 0.7056 1.4112 2.8224
24 Reserved 0.3528 0.5292 0.7056 1.0584 2.1168 4.2336
32 Reserved 0.4704 0.7056 0.9408 1.4112 2.8224 5.6448
48 0.3528 0.7056 1.0584 1.4112 2.1168 4.2336 8.4672
64 0.4704 0.9408 1.4112 1.8816 2.8224 5.6448 11.2896
96 0.7056 1.4112 2.1168 2.8224 4.2336 8.4672 16.9344
128 0.9408 1.8816 2.8224 3.7632 5.6448 11.2896 22.5792
192 1.4112 2.8224 4.2336 5.6448 8.4672 16.9344 Reserved
256 1.8816 3.7632 5.6448 7.5264 11.2896 22.5792 Reserved
384 2.8224 5.6448 8.4672 11.2896 16.9344 Reserved Reserved
512 3.7632 7.5264 11.2896 15.0528 22.5792 Reserved Reserved

In the controller mode of operation, the device uses the MD3 pin (as the system clock, CCLK) as the reference input clock source. The device provides flexibility in FSYNC selection with a supported system clock frequency option of either 256 × fS or 128 × fS or a fixed 48/44.1KSPS or 96/88.2KSPS as configured using the MD1 and MD2 pins. The table below shows the FSYNC and BCLK selection for the controller mode using the MD1 and MD2 pins.

Table 7-5 System Clock Selection for the Controller Mode
MD1 MD2 SYSTEM CLOCK SELECTION (Valid for Master Mode Only)
LOW LOW FSYNC = CCLK/256

I2S Mode:  BCLK = 64*fS

TDM Mode:
For FSYNC<=96KSPS, BCLK = 128*fS
For FSYNC>96KSPS, BCLK = 64*fS
LOW HIGH FSYNC = CCLK/128

I2S Mode: BCLK = 64*fS

TDM Mode:
For FSYNC<=96KSPS, BCLK = 128*fS
For FSYNC>96KSPS, BCLK = 64*fS
HIGH LOW FSYNC = 96/88.2KSPS;

I2S Mode: BCLK = 64*fS

TDM Mode: BCLK = 128*fS
HIGH HIGH FSYNC = 48/44.1KSPS;

I2S Mode: BCLK = 64*fS

TDM Mode: BCLK = 128*fS

See for the MD1, MD2 and MD3 pin function in the target mode of operation.