The design proceeds using the
techniques and tools suggested in the Design Methodology for MFB Filters in
ADC Interface Applications. The process includes:
- Scale the resistor values to not meaningfully contribute to the
output noise produced by the THS4552 by itself
- Select the RC ratios to hit the filter targets when reducing
the noise gain peaking within the filter design
- Set the output resistor to 10 Ω into a 2.2 nF differential
capacitor
- Add 100 pF common-mode capacitors to the load capacitor to
improve common noise filtering
- Inside the loop, add 20 Ω output resistors after the filter
feedback capacitor to increase the isolation to the load capacitor
- Include a place for a differential input capacitor (illustrated
as 100 fF in Figure 9-14)