SBOS831B December   2016  – June 2021 THS4552

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: (VS+) – (VS–) = 5 V
    6. 6.6 Electrical Characteristics: (VS+) – (VS–) = 3 V
    7. 6.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 6.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 6.9 Typical Characteristics: 3 V to 5 V Supply Range
  7. 7 Parameter Measurement Information
    1. 7.1 Example Characterization Circuits
    2. 7.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 7.3 Output Common-Mode Measurements
    4. 7.4 Differential Amplifier Noise Measurements
    5. 7.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 7.6 Simulated Characterization Curves
    7. 7.7 Terminology and Application Assumptions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential Open-Loop Gain and Output Impedance
      2. 8.3.2 Setting Resistor Values Versus Gain
      3. 8.3.3 I/O Headroom Considerations
      4. 8.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 8.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. 8.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      2. 8.4.2 Operation from a Differential Input to a Differential Output
        1. 8.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 8.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
      3. 8.4.3 Input Overdrive Performance
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Noise Analysis
      2. 9.1.2 Factors Influencing Harmonic Distortion
      3. 9.1.3 Driving Capacitive Loads
      4. 9.1.4 Interfacing to High-Performance Precision ADCs
      5. 9.1.5 Operating the Power Shutdown Feature
      6. 9.1.6 Channel-to-Channel Crosstalk
      7. 9.1.7 Channel-to-Channel Mismatch
      8. 9.1.8 Designing Attenuators
      9. 9.1.9 The Effect of Adding a Feedback Capacitor
    2. 9.2 Typical Applications
      1. 9.2.1 An MFB Filter Driving an ADC Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Differential Transimpedance Output to a High-Grade Audio PCM DAC Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Thermal Analysis
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations
    2. 11.2 Layout Example
    3. 11.3 EVM Board
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 TINA-TI Simulation Model Features
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics: (VS+) – (VS–) = 3 V

at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50 Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); specifications are per channel; see Figure 7-1 for a gain of 1-V/V test circuit
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST
LEVEL(1)
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 20 mVPP, G = 1, peaking (< 1.0 dB) 150 MHz C
VOUT = 20 mVPP, G = 2 80 C
VOUT = 20 mVPP, G = 10 14 C
GPB Gain-bandwidth product VOUT = 20 mVPP, G = 100 130 MHz C
LSBW Large-signal bandwidth VOUT = 1 VPP, G = 1 45 MHz C
Bandwidth for 0.1-dB flatness VOUT = 1 VPP, G = 1 14 MHz C
SR Slew rate(2) VOUT = 1 VPP, FPBW, G = 1 110 V/µs C
tR, tF Rise and fall time VOUT = 0.5 V step, G = 1, input tR = 4 ns 7.0 ns C
tSETTLE Settling time To 0.1%, VOUT = 0.5 V step, input tR = 4 ns, G = 1 35 ns C
To 0.01%, VOUT = 0.5 V step, input tR = 4 ns, G = 1 55 C
Overshoot and undershoot VOUT = 0.5 V step, G = 1, input tR = 4 ns 7% C
HD2 Second-order harmonic distortion f = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ –128 dBc C
f = 100 kHz, VOUT = 4 VPP, G = 1, RL = 1 kΩ –127 C
HD3 Third-order harmonic distortion f = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ –139 dBc C
f = 100 kHz, VOUT = 4 VPP, G = 1, RL = 1 kΩ –125 C
Input voltage noise f > 500 Hz, 1/f < 150 Hz 3.4 nV/√ Hz C
Input current noise f > 20 kHz, 1/f < 10 kHz 0.5 pA/√ Hz C
Overdrive recovery time G = 2, 2X output overdrive, dc coupled 100 ns C
Closed-loop output impedance f = 100 kHz (differential), G = 1 0.02 Ω C
Channel-to-channel crosstalk 2-VPP output on one channel, 1 MHz –80 dBc C
DC PERFORMANCE(5)
AOL Open-loop voltage gain ±2 V differential to 1 kΩ differential load 100 120 dB A
VIO Input-referred offset voltage TA = 25°C –175 ±40 175 µV A
TA = 0°C to +70°C –225 265 B
TA = –40°C to +85°C –295 295 B
TA = –40°C to +125°C –295 375 B
Input offset voltage drift(3) TA = –40°C to +125°C (PW package) –2.0 ±0.45 2.0 µV/°C B
Channel-to-channel input offset voltage mismatch TA = 25°C (PW package) –250 250 µV A
Input offset voltage drift mismatch TA = –40°C to +125°C (PW package) –2.6 2.6 µV/°C B
IIB Input bias current
(positive current out-of-node)		 TA = 25°C 1.0 1.5 µA A
TA = 0°C to +70°C 1.73 B
TA = –40°C to +85°C 1.80 B
TA = –40°C to +125°C 2.0 B
Input bias current drift(3) TA = –40°C to +125°C 2 3.3 5.5 nA/°C B
DC PERFORMANCE (continued)
IOS Input offset current TA = 25°C –50 ±10 50 nA A
TA = 0°C to +70°C –57 63 B
TA = –40°C to +85°C –68 67 B
TA = –40°C to +125°C –68 78 B
input offset current mismatch TA = 25°C –65 65 nA D
Input offset current drift(3) TA = –40°C to +125°C (PW package) –240 ±20 240 pA/°C B
Offset current drift mismatch TA = –40°C to +125°C (PW package) –260 ±20 260 pA/°C B
INPUT
Common-mode input, low > 87 dB CMRR at input range limits TA = 25°C (VS–) – 0.2 (VS–) – 0.1 V A
TA = –40°C to +125°C (VS–) – 0.1 VS– B
Common-mode input, high > 87 dB CMRR at input range limits TA = 25°C (VS+) – 1.2 (VS+) –1.1 V A
TA = –40°C to +125°C (VS+) – 1.3 (VS+) –1.2 B
CMRR Common-mode rejection ratio Input pins at [(VS+) – (VS–)] / 2 90 110 dB A
Input impedance differential mode Input pins at [(VS+) – (VS–)] / 2 100 || 1.2 kΩ || pF C
OUTPUT
VOL Output voltage, low TA = 25°C (VS–) + 0.2 (VS–) + 0.21 V A
TA = –40°C to +125°C (VS–) + 0.2 (VS–) + 0.22 B
VOH Output voltage, high TA = 25°C (VS+) – 0.21 (VS+) – 0.2 V A
TA = –40°C to +125°C (VS+) – 0.22 (VS+) – 0.2 B
Continuous output current ±1.5 V, RL = 40 Ω,
VOCM offset < ±20 mV		 TA = 25°C ±35 ±40 mA A
±1.3 V, RL = 40 Ω,
VOCM offset < ±20 mV		 TA = –40°C to +125°C ±30 B
Linear output current ±1.5 V, RL = 50 Ω,
AOL > 80 dB		 TA = 25°C ±28 ±35 mA A
±1.1 V, RL = 50 Ω,
AOL > 80 dB		 TA = –40°C to +125°C ±20 B
POWER SUPPLY
Specified operating voltage 2.7 3 5.4 V B
IQ Quiescent operating current per channel TA ≈ 25°C(6), VS+ = 3 V 1.24 1.31 1.40 mA A
TA = –40°C to +125°C, VS+ = 3 V 0.96 1.84 B
Supply current at minimum operating supply per channel TA = 25°C, VS+ = 2.7 V 1.24 1.28 1.38 mA D
dIQ/dT Quiescent current temperature coefficient per channel VS+ = 3 V 2.0 3.4 5.0 µA/°C B
±PSRR Power-supply rejection ratio Either supply pin to differential VOUT 90 105 dB A
POWER-DOWN
Enable voltage threshold Specified on above (VS–) + 1.15 V (VS–) + 1.15 V A
Disable voltage threshold Specified off below (VS–) + 0.55 V (VS–) + 0.55 V A
Disable pin bias current PD = VS– → VS+ –100 ±10 100 nA A
IQ(PD) Power-down quiescent current –2 1 5 µA A
tON Turn-on time delay Time from PD = low to VOUT = 90% of final value 750 ns C
tOFF Turn-off time delay Time from PD = low to VOUT = 10% of final value 150 ns C
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL(4) (see Figure 7-5)
SSBW Small-signal bandwidth VOCM = 100 mVPP at the control pin 40 MHz C
LSBW Large-signal bandwidth VOCM = 1 VPP at the control pin 8 MHz C
SR Slew rate(2) From 1-VPP LSBW 12 V/µs C
Output common-mode noise VOCM pin driven from low impedance, f ≥ 2 kHz 15 nV/√ Hz
Gain VOCM control pin input to output average voltage (see Figure 7-5) 0.997 0.999 1.001 V/V A
DC output balance (differential mode to common-mode output) VOUT = ±1 V 85 dB C
Output balance SSBW VOUT = 100 mVPP (output balance drops –3 dB from the 85 dB dc level) 300 kHz C
LSBW VOUT = 1 VPP (output balance drops –3 dB from the 85 dB dc level) 300 C
Input bias current –100 ±10 100 nA A
Input impedance 150 || 7 kΩ || pF C
Default voltage offset from
[(VS+) – (VS–)] / 2		 VOCM pin open –15 ±2 15 mV A
Default voltage offset drift from
[(VS+) – (VS–)] / 2		 TA = –40°C to +125°C 15 35 55 µA/°C B
CM VOS Common-mode offset voltage VOCM input driven to [(VS+) – (VS–)] / 2 TA = 25°C –5.0 ±1 5.0 mV A
TA = 0°C to +70°C –5.25 5.5 B
TA = –40°C to +85°C –5.7 5.6 B
TA = –40°C to +125°C –5.7 6.0 B
Common-mode offset voltage drift(3) VOCM input driven to [(VS+) – (VS–)] / 2 –10 ±2 10 µV/°C B
Common-mode headroom to negative supply –PSRR test (supply to VOD) –PSRR > 80 dB 0.55 V C
Common-mode loop supply headroom to negative supply < ±15 mV shift from mid-supply CM VOS TA = 25°C 0.55 V A
TA = 0°C to +70°C 0.6 B
TA = –40°C to +85°C 0.65 B
TA = –40°C to +125°C 0.7 B
Common-mode headroom to positive supply +PSRR test (supply to VOD) +PSRR > 80 dB 0.55 V C
Common-mode loop supply headroom to positive supply < ±15 mV shift from mid-supply CM VOS TA = 25°C 1.2 V A
TA = 0°C to +70°C 1.25 B
TA = –40°C to +85°C 1.3 B
TA = –40°C to +125°C 1.3 B
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at TA ≈ 25°C. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VPP / √ 2) × 2π × f–3dB.
(3) Input offset voltage drift, input bias current drift, and input offset current drift are the mean ±1-sigma values calculated by taking measurements at the maximum-range ambient temperature end points, computing the difference, and dividing by the temperature range. Maximum drift specifications are set by mean ±4 σ on the device distributions tested over a –40°̊C to +125°̊C ambient temperature range. Drift is not specified by final ATE testing or QA sample test.
(4) Specifications are from input VOCM pin to differential output average voltage.
(5) Currents out of pin are treated as a positive polarity.
(6) TA = 25°C and ICC ≈ 1.31 mA. The test limit is expanded for the ATE ambient range of 22°C to 32°C with a 4 µA/°C ICC temperature coefficient considered; see Figure 10-1.