SBOSA41A May   2023  – September 2023 TMP4718

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 1.2-V Logic Compatible Inputs
      2. 8.3.2 Series Resistance Cancellation
      3. 8.3.3 Device Initialization, Resistor Decoding, and Default Temperature Conversion
      4. 8.3.4 Adjustable Default T_CRIT High-Temperature Limit
      5. 8.3.5 ALERT and T_CRIT Output
      6. 8.3.6 Fault Queue
      7. 8.3.7 Filtering
      8. 8.3.8 One-Shot Conversions
    4. 8.4 Device Functional Modes
      1. 8.4.1 Interrupt and Comparator Mode
        1. 8.4.1.1 Interrupt Mode
        2. 8.4.1.2 Comparator Mode
        3. 8.4.1.3 T_CRIT Output
      2. 8.4.2 Shutdown Mode
      3. 8.4.3 Continuous Conversion Mode
    5. 8.5 Programming
      1. 8.5.1 Temperature Data Format
      2. 8.5.2 I2C and SMBus Interface
      3. 8.5.3 Device Address
      4. 8.5.4 Bus Transactions
        1. 8.5.4.1 Writes
        2. 8.5.4.2 Reads
      5. 8.5.5 SMBus Alert Mode
    6. 8.6 Register Map
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

SMBus Alert Mode

When bit 0 of the Filter_Alert_Mode Register is set to 0, the Interrupt/ SMBus Alert mode is enabled. In this mode, the ALERT pin is asserted at the end of a conversion cycle if the measured temperature exceeds a High Alert Limit or goes below a Low Alert Limit defined in the limit registers. In this mode, the TMP4718 sets the ALERT mask bit of the Configuration Register during a read of the Status Register if any flag in Status Register, except the ADC_Busy flag and Remote Diode Open flag, is set. This prevents the ALERT pin from triggering until the controller resets the ALERT mask bit (write 0 to Alert_MSK bit).

The ALERT High Status flags set at the end of a conversion cycle when the measured temperature exceeds a High Alert Limit register limit. There are separate High Limit values and status register flags for the remote and local temperature measurements. The status register flags will only set to their respective temperature measurements.

The Remote ALERT Low Status flag sets at the end of a conversion cycle when the measured remote temperature is below the Remote Low Alert Limit register limit.

The Status Register limit flags are cleared after a read command of the Status Register from the controller and are set again at the end of a proceeding temperature conversion cycle if the measured temperature is outside the set limits.

When the ALERT pin is connected to the SMBus alert line, there can be multiple devices on the same output. For the controller to resolve which target is generating an alert, the controller can send a SMBus ALERT Response Address (ARA) command. If the TMP4718 is generating an alert and an ARA command is sent, the TMP4718 sets the ALERT MASK bit in the Configuration register and send the target address to the controller. An ARA command will not clear any Status register flags.

Figure 8-15 shows the behavior of the ALERT pin and flags while in SMBus Alert mode.

GUID-20210325-CA0I-F7HH-3CSK-HSG4J51SQQMF-low.svg Figure 8-15 Alert SMBus Mode Timing Diagram