SLASF51 February 2024 TMUXHS4446
PRODUCTION DATA
Figure 7-5 through Figure 7-8 illustrate DisplayPort 1.4 Tx compliance results at HBR3 8.1Gbps. Eye diagrams (in scope, no cable model) are compared from the baseline setup and from the same setup plus TMUXHS4446 board. The diagrams are for lane 0. Other lanes also result in to similar eye diagrams. Jitter degradation through TMUXHS4446 is minimal.
Figure 7-9 through Figure 7-12 illustrate USB 3.x Gen2 Tx compliance results at 10Gbps. Eye diagrams (in scope, near end) are compared from the baseline setup and from the same setup plus TMUXHS4446 board. The diagrams are for lane 0. Other lanes also result in to similar eye diagrams. Jitter degradation through TMUXHS4446 is minimal.