SLVSDN7B August   2016  – February 2022 TPD1E10B06-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2.     ESD Ratings - AEC Specification
    3. 6.2 ESD Ratings—IEC Specification
    4. 6.3 ESD Ratings—ISO Specification
    5. 6.4 Recommended Operating Conditions
    6. 6.5 Thermal Information
    7. 6.6 Electrical Characteristics
    8. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  AEC-Q101 Qualified
      2. 7.3.2  IEC 61000-4-2 ESD Protection
      3. 7.3.3  ISO 10605 ESD Protection
      4. 7.3.4  IEC 61000-4-5 Surge Protection
      5. 7.3.5  IO Capacitance
      6. 7.3.6  Dynamic Resistance
      7. 7.3.7  DC Breakdown Voltage
      8. 7.3.8  Ultra Low Leakage Current
      9. 7.3.9  Clamping Voltage
      10. 7.3.10 Industrial Temperature Range
      11. 7.3.11 Space-Saving Footprint
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
VRWM Reverse stand-off voltage Pin 1 to 2 or Pin 2 to 1 5.5 V
ILEAK Leakage current Pin 1 = 5 V, Pin 2 = 0 V 100 nA
VClamp1,2 Clamp voltage with surge strike on pin 1, pin 2 grounded. IPP = 1 A, tp = 8/20 µs(2) 10 V
VClamp1,2 Clamp voltage with surge strike on pin 1, pin 2 grounded. IPP =5 A, tp = 8/20 µs(2) 14 V
VClamp2,1 Clamp voltage with surge strike on pin 2, pin 1 grounded. IPP = 1 A, tp = 8/20 µs(2) 8.5 V
VClamp2,1 Clamp voltage with surge strike on pin 2, pin 1 grounded. IPP =5 A, tp = 8/20 µs(2) 14 V
RDYN Dynamic resistance Pin 1 to Pin 2(1) 0.32 Ω
Pin 2 to Pin 1(1) 0.38
CIO I/O capacitance VIO = 2.5 V;  ƒ = 1 MHz  12 pF
VBR1,2 Break-down voltage, pin 1 to pin 2 IIO = 1 mA 6 V
VBR2,1 Break-down voltage, pin 2 to pin 1 IIO = 1 mA 6 V
(1) Extraction of RDYN using least squares fit of TLP characteristics between IPP = 10 A and IPP = 20 A.
(2) Nonrepetitive current pulse 8 to 20 µs exponentially decaying waveform according to IEC 61000-4-5