SLVSC33A August   2013  – October 2022 TPS54625

PRODUCTION DATA  

  1. 1 FEATURES
  2. 2 APPLICATIONS
  3. 3 DESCRIPTION
  4. 4 ORDERING INFORMATION (1)
  5. 5 ABSOLUTE MAXIMUM RATINGS
  6. 6 THERMAL INFORMATION
  7. 7 RECOMMENDED OPERATING CONDITIONS
  8. 8 ELECTRICAL CHARACTERISTICS
  9. 9 DEVICE INFORMATION
  10. 10OVERVIEW
  11. 11DETAILED DESCRIPTION
    1. 11.1 PWM Operation
    2. 11.2 PWM Frequency and Adaptive On-Time Control
    3. 11.3 Soft Start and Pre-Biased Soft Start
    4. 11.4 Power Good
    5. 11.5 Output Discharge Control
    6. 11.6 Current Protection
    7. 11.7 Over/Under Voltage Protection
    8. 11.8 UVLO Protection
    9. 11.9 Thermal Shutdown
  12. 12TYPICAL CHARACTERISTICS
  13. 13DESIGN GUIDE
    1. 13.1 Step By Step Design Procedure
    2. 13.2 Output Voltage Resistors Selection
    3. 13.3 Output Filter Selection
    4. 13.4 Input Capacitor Selection
    5. 13.5 Bootstrap Capacitor Selection
    6. 13.6 VREG5 Capacitor Selection
  14. 14THERMAL INFORMATION
  15. 15LAYOUT CONSIDERATIONS
  16. 16Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1 PWM Operation

The main control loop of the TPS54625 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control.