SLVSC33A August   2013  – October 2022 TPS54625

PRODUCTION DATA  

  1. 1 FEATURES
  2. 2 APPLICATIONS
  3. 3 DESCRIPTION
  4. 4 ORDERING INFORMATION (1)
  5. 5 ABSOLUTE MAXIMUM RATINGS
  6. 6 THERMAL INFORMATION
  7. 7 RECOMMENDED OPERATING CONDITIONS
  8. 8 ELECTRICAL CHARACTERISTICS
  9. 9 DEVICE INFORMATION
  10. 10OVERVIEW
  11. 11DETAILED DESCRIPTION
    1. 11.1 PWM Operation
    2. 11.2 PWM Frequency and Adaptive On-Time Control
    3. 11.3 Soft Start and Pre-Biased Soft Start
    4. 11.4 Power Good
    5. 11.5 Output Discharge Control
    6. 11.6 Current Protection
    7. 11.7 Over/Under Voltage Protection
    8. 11.8 UVLO Protection
    9. 11.9 Thermal Shutdown
  12. 12TYPICAL CHARACTERISTICS
  13. 13DESIGN GUIDE
    1. 13.1 Step By Step Design Procedure
    2. 13.2 Output Voltage Resistors Selection
    3. 13.3 Output Filter Selection
    4. 13.4 Input Capacitor Selection
    5. 13.5 Bootstrap Capacitor Selection
    6. 13.6 VREG5 Capacitor Selection
  14. 14THERMAL INFORMATION
  15. 15LAYOUT CONSIDERATIONS
  16. 16Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

15 LAYOUT CONSIDERATIONS

  1. A top side area should be filled with ground as much as possible due to relatively higher current output device.
  2. The ground area under the device thermal pad should be large as possible and directly connect to the thermal pad. Also 2nd, 3rd and 4th PCB layer should be connected to ground directly from the thermal pad.
  3. Keep the input switching current loop as small as possible.
  4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback pin of the device.
  5. Keep analog and non-switching components away from switching components.
  6. Make a single point connection from the signal ground to power ground.
  7. Do not allow switching current to flow under the device.
  8. Keep the pattern lines for VIN and PGND broad.
  9. Exposed pad of device must be connected to PGND with solder.
  10. VREG5 capacitor should be placed near the device, and connected PGND.
  11. Output capacitor should be connected to a broad pattern of the PGND.
  12. Voltage feedback loop should be as short as possible, and preferably with ground shield.
  13. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.
  14. Providing sufficient via is preferable for VIN, SW and PGND connection.
  15. PCB pattern for VIN, SW, and PGND should be as broad as possible.
  16. VIN Capacitor should be placed as near as possible to the device.
GUID-8DC270BD-40B2-44EC-9852-446B628F376A-low.gifFigure 15-1 PCB Layout