SLVSEQ0A May   2019  – March 2020 TPS54A24

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Simplified Schematic
  3. 3 Description
    1.     Efficiency (VIN = 12 V, fSW = 500 kHz)
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Continuous Conduction Mode Operation (CCM)
      3. 7.3.3  VIN Pins and VIN UVLO
      4. 7.3.4  Voltage Reference and Adjusting the Output Voltage
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjustable UVLO
      7. 7.3.7  Soft Start and Tracking
      8. 7.3.8  Safe Start-Up Into Prebiased Outputs
      9. 7.3.9  Power Good
      10. 7.3.10 Sequencing (SS/TRK)
      11. 7.3.11 Adjustable Switching Frequency (RT Mode)
      12. 7.3.12 Synchronization (CLK Mode)
      13. 7.3.13 Bootstrap Voltage and 100% Duty Cycle Operation (BOOT)
      14. 7.3.14 Output Overvoltage Protection (OVP)
      15. 7.3.15 Overcurrent Protection
        1. 7.3.15.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.15.2 Low-Side MOSFET Overcurrent Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Output Voltage Resistors Selection
        7. 8.2.2.7  Soft-Start Capacitor Selection
        8. 8.2.2.8  Undervoltage Lockout Setpoint
        9. 8.2.2.9  Bootstrap Capacitor Selection
        10. 8.2.2.10 PGOOD Pullup Resistor
        11. 8.2.2.11 Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.11 Compensation

There are several methods used to compensate DC/DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation internal to the device. Because the slope compensation is ignored, the actual cross-over frequency will usually be lower than the cross-over frequency used in the calculations. This method assumes the cross-over frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole. This is the case when using low ESR output capacitors. Use the WEBENCH® software for more accurate loop compensation. These tools include a more comprehensive model of the control loop.

To get started, the modulator pole, fpmod, and the ESR zero, fzmod must be calculated using Equation 27 and Equation 28. For COUT, use a derated value of 192 μF and an ESR of 0.7 mΩ. Use equations Equation 29 and Equation 30, to estimate a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is 7.2 kHz and fzmod is 1940 kHz. Equation 29 is the geometric mean of the modulator pole and the ESR zero. Equation 30 is the mean of modulator pole and one half the switching frequency. Equation 29 yields 118 kHz and Equation 30 yields 42.4 kHz. Use the lower value of Equation 29 or Equation 30 for an initial crossover frequency. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole.

Equation 27. TPS54A24 eq43_lvs795.gif

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Equation 28. TPS54A24 eq44_lvs795.gif

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Equation 29. TPS54A24 eq45_lvs919.gif

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Equation 30. TPS54A24 eq46_lvs919.gif

To determine the compensation resistor (RCOMP = R5) use Equation 31. RCOMP is calculated to be 5.26 kΩ and the closest standard value 5.23 kΩ. Use Equation 32 to set the compensation zero to the modulator pole frequency. Equation 32 yields 2120 pF for compensating capacitor (CCOMP = C14); round this up to the next standard value of 2200 pF.

Equation 31. TPS54A24 Rcomp_SCO3.gif

where

  • Power stage transconductance, gmPS = 17 A/V
  • VOUT = 1.8 V
  • VREF = 0.6 V
  • Error amplifier transconductance, gmEA = 1100 µA/V
Equation 32. TPS54A24 Ccomp_SCO3.gif

A compensation pole is implemented using an additional capacitor (CHF = C13) in parallel with the series combination of RCOMP and CCOMP. This capacitor is recommended to help filter any noise that may couple to the COMP voltage signal. Use the larger value of Equation 33 and Equation 34 to calculate the CHF and to set the compensation pole. CHF is calculated to be the largest of 16 pF and 112 pF. Round this down to the next standard value of 100 pF.

Equation 33. TPS54A24 Chfesr_SCO3.gif

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Equation 34. TPS54A24 Chffsw_SCO3.gif

Type III compensation can be used by adding the feed forward capacitor (CFF = C15) in parallel with the upper feedback resistor. Type III compensation adds phase boost above what is possible from type II compensation because it places an additional zero/pole pair. The zero/pole pair is not independent. As a result once the zero location is chosen, the pole is fixed as well. The zero is placed at 1/2 the fSW by calculating the value of CFF with Equation 35. The calculated value is 53 pF — round this down to the closest standard value of 47 pF. It is possible to use larger feedforward capacitors to further improve the transient response but take care to ensure there is a minimum of -10 dB gain margin at 1/2 the fSW in all operating conditions. The feedforward capacitor injects noise on the output into the FB pin and this added noise can result in more jitter at the switching node. To little gain margin can cause a repeated wide and narrow pulse behavior.

Equation 35. TPS54A24 EQ_Cff_SLVSDV8.gif

The initial compensation based on these calculations is RCOMP = 5.23 kΩ, CCOMP = 2200 pF, CHF = 100 pF and CFF = 47 pF. These values yield a stable design but after testing the real circuit these values were changed to target a higher crossover frequency to improve transient response performance. The crossover frequency is increased by increasing the value of R5 and decreasing the value of the compensation capacitors. The final values used in this example are RCOMP = 10.0 kΩ, CCOMP = 2700 pF, CHF = 22 pF and CFF = 100 pF.