9.3.1 LED High-current Regulators, Unused Inputs

The TPS6132x device uses LED forward voltage sensing circuitry on LEDx pins to optimize the power stage boost ratio for maximum efficiency. TI recommends against leaving any of the LEDx pins unused if the operation is selected through ENDLED[3:1] bits due to the nature of the sensing circuitry. Leaving these pins unconnected, whilst the respective ENLEDx bits have been set, forces the control loop into high gain and eventually trip the output over-voltage protection.

The LEDx inputs may be connected together to drive one or two LEDs at higher currents. Connecting the current sink inputs in parallel does not affect the internal operation of the TPS6132x. TI recommends disabling the LED inputs that are not used for best operation (see REGISTER5 (address = 0x05)).

To achieve smooth LED current waveforms, the TPS6132x device actively controls the LED current ramp-up and ramp-down sequences.

Figure 31. LED Current Slew-Rate Control

In high-current mode (HC_SEL = 1), the LED current settings are defined as a fixed ratio (×2.25) versus the direct drive mode values (HC_SEL = L).

9.3.2 Safety Timer Accuracy

The LED strobe timer uses the internal oscillator as a reference clock. The timer execution speed (see REGISTER3 (address = 0x03)) scales according to the reference clock accuracy.

9.3.3 Current Limit Operation

The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the off-time through sensing of the voltage drop across the synchronous rectifier. The detection threshold is user selectable through the ILIM bit. The ILIM bit can only be set while still in shutdown before the device begins operation..

Figure 32 illustrates the inductor and rectifier current waveforms during current limit operation. The output current (I_OUT) is the average of the rectifier ripple current waveform. When the load current is increased such that the lower peak is above the current limit threshold, the off-time is lengthened to allow the current to decrease to this threshold before the next on-time begins, so called frequency fold-back mechanism.

Both the output voltage and the switching frequency are reduced as the power stage of the device operates in a constant current mode. Equation 1 shows the maximum continuous output current (I_OUT(CL)) before entering current limit operation.

Equation 1.

The TPS6132x device also provides a negative current limit (approximately 300 mA) to prevent an excessive reverse inductor current when the power stage sinks current from the output (storage capacitor) in the forced continuous conduction mode.

Figure 32. Inductor and Rectifier Currents in Current Limit Operation

9.3.4 Start-Up Sequence

To avoid high inrush current during start-up, the internal start-up cycle begins with a precharge phase. During precharge, the rectifying switch is turned on until the output capacitor is either charged to a value close to the input voltage or approximately 3.3 V, whichever occurs first. The rectifying switch is current limited during this phase. The current limit increases with decreasing input to output voltage difference. This circuit also limits the output current under short-circuit conditions at the output. Figure 33 shows the typical precharge current vs input minus the output voltage for a specific input voltage.

Figure 33. Typical DC Precharge and Short-Circuit Current

In direct drive mode (HC_SEL = L, TPS6132x), after having precharged the output capacitor, the device begins switching and increases its current limit in three steps to the target determined by the ILIM setting, typically to 30 mA, 250 mA, or full current limit. The current limit transition from the first to the second step occurs after a milli-second of operation. Full current limit operation is set once the output voltage reaches its regulation limits. In this mode, the active balancing circuit is disabled.

In high-current mode (HC_SEL = H), the precharge voltage of the storage capacitor is dependent on the input voltage and operating mode (voltage regulation versus current regulation mode). In case the device is set for exclusive current regulation operation (MODE_CTRL = 01 or 10 and ENVM = 0), the output capacitor precharge voltage is close to the input voltage. Under all other operating conditions, the precharge voltage is either close to the input voltage or approximately 3.3 V, whichever is lower. Furthermore, precharge operation can be suspended and resumed through the Tx-MASK input (see REGISTER4 (address = 0x04) and REGISTER3 (address = 0x03)).

The device begins switching after the storage capacitor pre-charging is complete. During down-mode operation, the inductor valley current is actively limited either to 30 mA or 250 mA (see REGISTER4 (address = 0x04)). As the device enters boost mode operation, the current limit transitions to full capacity (see REGISTER4 (address = 0x04) and REGISTER3 (address = 0x03)). As a consequence, the output voltage ramps-up linearly and the start-up time required to reach the programmed output voltage (see REGISTER6 (address = 0x06)) depends primarily on the super-capacitor value and load current. In this mode, the active balancing circuit is enabled.

9.3.5 Power Good (Flash Ready)

The TPS6132x integrates a power-good circuitry that is activated when the device is operating in voltage regulation mode (MODE_CTRL = 11 or ENVM = 1). In shutdown mode (MODE_CTRL = 00) the GPIO/PG pin state is defined in Table 5.

Depending on the GPIO/PG output stage type selection, push-pull or open-drain, the polarity of the power-good output signal (PG) can be inverted or noninverted. The power-good software bit and hardware signal polarity is defined in Table 6.

The power good signal is valid when the output voltage is within –1.5% and 2.5% of its nominal value. Conversely, it is asserted low when the voltage mode operation gets suspended (MODE_CTRL ≠ 11 and ENVM = 0).

Figure 34. Power Good Operation (DIR = 1, GPIOTYPE = 1)

The TPS6132x device uses a control architecture that allows recycling excessive energy that might be stored in the output capacitor. By reversing the operation of the boost power stage, the converter is able to transfer energy from its output back into the input source. In this case, the power-good signal is deasserted while the output voltage is decreasing towards its target value: the closest fit voltage the converter can support. See Down Mode In Voltage Regulation Mode for additional information.

9.3.6 LED Temperature Monitoring

The TPS6132x devices monitor the LED temperature by measuring the voltage between the TS and AGND pins. An internal current source provides the bias (approximately 24 μA) for a negative-temperature coefficient resistor (NTC), and the TS pin voltage is compared to internal thresholds (1.05 V and 0.345 V) to protect the LEDs against overheating.

The temperature monitoring related blocks are always active in DC-light or flashlight modes. In voltage mode operation (MODE_CTRL = 11), the device only activates the TS input when the ENTS bit is set to high. In shutdown mode, the LED temperature supervision is disabled and the quiescent current of the device is dramatically reduced.

The LEDWARN and LEDHOT bits reflect the LED temperature. The LEDWARN bit is set when the voltage seen at the TS pin is lower than 1.05 V. This threshold corresponds to an LED warning temperature value, the device operation is still permitted.

While regulating LED current (DC-light or flashlight modes), the LEDHOT bit is latched when the voltage seen at the TS pin is lower than 0.345 V. This threshold corresponds to an excessive LED temperature value, the device operation is immediately suspended (MODE_CTRL bits are reset and HOTDIE bits are set).

9.3.7 Hot Die Detector

The hot die detector monitors the junction temperature but does not shutdown the device. It provides an early warning to the camera engine to avoid excessive power dissipation thus preventing thermal shutdown during the next high-power flash strobe.

The hot die detector (HOTDIE bits) reflects the instantaneous junction temperature and is always enabled, except when the device is in shutdown mode (MODE_CTRL = 00).

9.3.8 Undervoltage Lockout

The undervoltage lockout circuit (UVLO) protects the device from mis-operation at low input voltages by preventing the converter from turning on the switch-MOSFET or rectifier-MOSFET for battery voltages below 2.3 V. The I²C compatible interface is fully functional down to 2.1-V input voltage.

9.3.9 Storage Capacitor Active Cell Balancing

A fully charged super-capacitor typically has a leakage current under 1 μA. The TPS6132x device integrates an active balancing feature to cut the total leakage current from the super-capacitor and balance circuit to less than 1.7 μA (typical).

The device integrates a window comparator to monitor the tap point of the multi-cell super-capacitor. The balancing output (BAL) is substantially half the actual output voltage (V_OUT). If the internal leakage current in one capacitor is larger than in the other, the voltage at their junction tends to change in such a way that the voltage on the capacitor with the larger (or largest) leakage current is reduced.

When this happens, current flows from BAL in an appropriate direction to reduce the magnitude of voltage changes. After a long period of steady-state conditions the current from BAL is approximately equal to the difference between the leakage currents of the capacitor pair being balanced by the circuit. The output resistance of the balancing circuit, approximately 250 Ω, determines how quickly an imbalance is corrected.

9.3.10 RED Light Privacy Indicator

The TPS6132x device provides a high-side linear constant current source to drive low VF LEDs. The LED current is directly regulated off the battery and can be controlled through the INDC bits. Operation is understood best by referring to the Figure 35 and Figure 36.

Figure 35. RED Light Indicator, Configuration 1

Figure 36. RED Light Indicator, Configuration 2

The device can provide a path to allow for reverse biasing of white LEDs (see Figure 36). To do so, the output of the converter (VOUT) is pulled to ground thus allowing a reverse current to flow. This mode of operation is only possible when the converter’s power stage is in shutdown (MODE_CTRL = 00, ENVM = 0 and HC_SEL = 0).

9.3.11 White LED Privacy Indicator

The TPS6132x device features white LED drive capability at low light intensity. To generate a reduced LED average current, the device employs a 30-kHz fixed frequency PWM modulation scheme. The PWM timer uses the internal oscillator as reference clock, therefore the PWM modulating frequency shows the same accuracy as the internal reference clock. See Figure 30 for more information on device operation.

The DC-light current is modulated with a duty cycle defined by the INDC bits. The low light dimming mode can only be activated in the software controlled DC-light only mode (MODE_CTRL = 01, ENVM = 1) and applies to the LEDs selected through ENLED bits. In this mode, the DC-light safety timeout feature is disabled.

Figure 37. PWM Dimming Principle

9.3.12 Storage Capacitor, Precharge Voltage Calibration

High-power LEDs tend to exhibit a wide forward voltage distribution. The TPS6132x device integrates a self-calibration procedure that can be used to determine the optimum super-capacitor precharge voltage based on the actual worst case LED forward voltage and ESR of the storage capacitor. This calibration procedure is meant to start at a minimum output voltage and can be initiated by setting the SELFCAL bit, preferably with MODE_CTRL = 00, ENVM = 0.

The calibration procedure monitors the sense voltage across the low-side current regulators, according to ENLED bits setting, and registers the LED featuring the largest forward voltage. The TPS6132x device automatically sweeps through its output voltage range and performs a short duration flash strobe for each step (see REGISTER2 (address = 0x02) and REGISTER1 (address = 0x01)).

In direct drive mode (HC_SEL = L), the energy is being directly transferred from the battery to the LEDs. In high-current mode (HC_SEL = H), the energy is supplied exclusively by the output reservoir capacitor and the inductive power stage is turned off for the flash strobe period of time.

The sequence is stopped once each of the the low-side current regulators has enough headroom voltage, typically 400 mV. The resulting output voltage is written to register OV and the SELFCAL bit is set. The SELFCAL bit is only reset at the start of a calibration cycle. When SELFCAL is asserted, the output voltage register (OV) returns the result of the last calibration sequence.

Figure 38. LED Forward Voltage Self-Calibration Principle

9.3.13 Storage Capacitor, Adaptive Precharge Voltage

In high-power LED camera flash applications, the storage capacitor is supposed to be charged to an optimum voltage level to:

• Maintain sufficient headroom voltage across the LED current regulators for the entire strobe time.
• Minimize the power dissipation in the device.

High-power LEDs tend to exhibit large dynamic forward voltage variation relating to own self-heating effects. In addition, the energy storage capacitor, an electrochemical double-layer capacitor or super-capacitor, also shows a relatively large effective capacitance and ESR spread. The main factors contributing to these variations are: flash strobe duration, temperature, and ageing effects.

In practice, it normally becomes very challenging to compensate for all these variations and a worst-case design would presumably be too pessimistic. As a consequence, designers would have to give-up on the benefits coming along with the Storage Capacitor, Precharge Voltage Calibration approach.

The TPS6132x device offers the possibility of controlling the storage capacitor precharge voltage in a closed-loop manner. The principle is to dynamically adjust the initial pre-voltage to the minimum value, as required for the particular components characteristic and operating conditions.

The reference criteria used to evaluate proper operation is the headroom voltage across the LED current regulators. In case of a critical headroom voltage (V_LEDx) at the end of a flash strobe, cycle n, the precharge voltage must be increased before to the next capture sequence, cycle n + 1.

Figure 39. Storage Capacitor, Simple Adaptive Precharge Voltage

9.3.14 Serial Interface Description

I²C is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors [1]. The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and transmits data on the bus under control of the master device.

The TPS6132x device works as a slave and supports the following data transfer modes, as defined in the I²C-Bus Specification [1]: standard mode (100 kbps) and fast mode (400 kbps), and high-speed mode (3.4 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as supply voltage remains above 2.1 V.

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as HS-mode. The TPS6132x device supports 7-bit addressing; 10-bit addressing and general call address are not supported. The device 7-bit address is defined as ‘011 0011’ (TPS61325) and ‘011 0010’ (TPS61326).

9.3.14.1 F/S-Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 40. All I²C-compatible devices must recognize a start condition.

Figure 40. START and STOP Conditions

The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit (R/W) on the SDA line. The master ensures that data is valid during all transmissions. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 41). All devices receive the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 42) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave is established.

Figure 41. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8 data bits and a 1-bit acknowledge can continue as long as necessary.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 40). This releases the bus and stops the communication link with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address.

Figure 42. Acknowledge on the I²C Bus

Figure 43. Bus Protocol

9.4.1 Down Mode In Voltage Regulation Mode

In general, a boost converter only regulates output voltages which are higher than the input voltage. The featured devices come with the ability to regulate 4.2 V at the output with an input voltage as high as 5.5 V. To control these applications properly, a down conversion mode is implemented.

In voltage regulation mode, if the input voltage reaches or exceeds the output voltage, the converter changes to the down-conversion mode. In this mode, the control circuit changes the behavior of the rectifying PMOS. It sets the voltage drop across the PMOS as high as necessary to regulate the output voltage. This means the power losses in the converter increase. This must be taken into account for thermal consideration. The down conversion mode is automatically turned off as soon as the input voltage falls about 200 mV below the output voltage.

For proper operation in down conversion mode the output voltage must not be programmed higher than approximately 5.3 V. Take care not to violate the absolute maximum ratings at the SW pins.

The TPS6132x device uses a control architecture that allows recycling excessive energy that might be stored in the output capacitor. By reversing the operation of the boost power stage, the converter is capable of transferring energy from its output back into the input source.

In high-current mode (HC_SEL = 1), this feature becomes useful to dynamically adjust the output voltage (V_OUT) depending on the operating conditions. For example, 4.95 V constant output voltage to support audio applications or variable storage capacitor precharge voltage, see Figure 76.

This reverse operating mode can only perform within an output voltage range higher than the input supply. For example, if the storage capacitor is initially precharged to 4.95 V, the input voltage is around 4.1 V and the target output voltage is set to 3.825 V, the converter is only able to lower the output node down to the input level.

9.4.2 Power-Save Mode Operation, Efficiency

The TPS6132x device integrates a power save mode to improve efficiency at light load. In power save mode the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with one or several pulses and goes again into power save mode once the output voltage exceeds the set threshold voltage.

Figure 44. Operation in PFM Mode and Transfer to PWM Mode

The power save mode can be enabled and disabled through the ENPSM bit. In down conversion mode, power save mode is always active and the device cannot be forced into fixed frequency operation at light loads.

The LED sense voltage has a direct effect on the converter’s efficiency. Because the voltage across the low-side current regulator does not contribute to the output power, LED brightness, reducing the sense voltage increases the efficiency of the device.

In direct drive mode (HC_SEL = L), the energy is being directly transferred from the battery to the LEDs. The integrated current control loop automatically selects the minimum boosting ratio to maintain regulation based on the LED forward voltage and current requirements. The low-side current regulators drop the voltage difference between the input voltage and the LEDs forward voltage (V_F(LED) < V_IN). When running in boost mode (V_F(LED) > V_IN), the voltage present at the LEDx pins of the low-side current regulators is typically 400 mV, leading to high power conversion efficiency. Depending on the input voltage and the LEDs forward voltage characteristic, the converter shows efficiency in the range of about 75% to 90%.

In high-current mode (HC_SEL = H), the device is only supplying a limited amount of energy directly from the battery, for example, DC-light, contribution to flash current, or voltage regulation mode. During a flash strobe, the bulk of the energy supplied to the LEDs is provided by the reservoir capacitor. The low-side current regulators typically operate with 400-mV headroom voltage. This means the power losses in the device increase and thermal considerations become more important.

9.4.3 Mode Of Operation: DC-Light and Flashlight

Operation is understood best by referring to Figure 30. The device set to one of four different operating modes depending on the state of the MODE_CTRL bits.

• MODE_CTRL = 00: The device is in shutdown mode.
• MODE_CTRL = 01: The STRB0 and STRB1 inputs are disabled. The device is regulating the LED current in DC-light mode (DCLC bits) regardless of the STRB0 and STRB1 inputs and the START_FLASH/TIMER (SFT) bit. To avoid device shutdown by DC-light safety timeout, MODE_CTRL must be refreshed within less than 13 s (STRB1 = 0). The DC-light watchdog timer can be disabled by pulling the STRB1 signal high.
• MODE_CTRL = 10: The STRB0 and STRB1 inputs are enabled and the flashlight pulse can either be triggered by these synchronization signals or by a software command (START_FLASH/TIMER (SFT) bit, STRB0 = 1). The LEDs' operation is enabled or disabled according to the STRB0 and STRB1 inputs, the flashlight safety timer is activated and the DC-light safety timer is disabled.
• MODE_CTRL = 11: The device is regulating a constant output voltage according to OV bits' settings. The low-side LEDx current regulators are disabled and the LEDs are disconnected from the output. In this operating mode, the safety timer is disabled.

9.4.4 Flash Strobe Is Level Sensitive (STT = 0): LED Strobe Follows STRB0 and STRB1 Inputs

In this mode, the high-power LEDs are driven at the flashlight current level and the safety timer (STIM) is running. The maximum duration of the flashlight pulse is defined in the STIM register.

The safety timer is triggered on rising edge and stopped either by a negative logic on the synchronization source (STRB0 = STRB1 = 0) or by a timeout event (TO bit).

Figure 45. Hardware Synchronized DC-Light and Flashlight Strobe

9.4.5 Flash Strobe Is Leading Edge Sensitive (STT = 1): One-Shot LED Strobe

In this mode, the high-power LEDs are driven at the flashlight current level and the safety timer (STIM) is running. The duration of the flashlight pulse is defined in the STIM register.

The flashlight strobe is started either by a rising edge on the synchronization source (STRB0 = 1 and STRB1 = 0) or by a positive transition on the START-FLASH/TIMER (SFT) bit (STRB0 = 1 and STRB1 = 0). Once running, the timer ignores all kind of triggering signals and only stops after a timeout (TO). START-FLASH/TIMER (SFT) bit is being reset by the timeout (TO) signal.

Figure 46. Edge Sensitive Timer
(Single Trigger Event)

9.4.6 LED Failure Modes and Overvoltage Protection

If a high-power LED fails as a short circuit, the low-side current regulator limits the maximum output current and the HIGH-POWER LED FAILURE (HPLF) flag is set.

If a high-power LED fails as an open circuit, the control loop initially attempts to regulate off of its low-side current regulator feedback signal. This drives V_OUT higher. As the open circuited LED never accepts its programmed current, V_OUT must be voltage-limited by means of a secondary control loop.

The TPS6132x device limits V_OUT according to the overvoltage protection settings (see Figure 47). In this failure mode, V_OUT is either limited to 4.65 V (typical) or 6.0 V (typical) and the HIGH-POWER LED FAILURE (HPLF) flag is set.

See LED High-current Regulators, Unused Inputs for more information.

Figure 47. Overvoltage Protection Operation, 4.65 V (Typical)

9.4.7 Hardware Voltage Mode Selection

The TPS6132x device integrates a software control bit (ENVM) that can be used to force the converter to run in voltage mode regulation. Table 8 gives an overview of the different modes of operation.

9.4.8 Flashlight Blanking (Tx-MASK)

In direct drive mode (HC_SEL = 0), the Tx-MASK input signal can be used to disable the flashlight operation, for example, during a RF PA transmission pulse. This blanking function turns the LED from flashlight to DC-light thereby reducing almost instantaneously the peak current loading from the battery. The Tx-MASK function has no influence on the safety timer duration.

Figure 48. Synchronized Flashlight With Blanking Periods (STRB1 = 0)

In high-current mode (HC_SEL = 1), the Tx-MASK input pin is also used to dynamically adjust the device’s current limit setting, controlling the maximum current drawn from the input source. See Current Limit Operation for additional information.

9.4.9 Shutdown

Pulling the MODE_CTRL bits low forces the device into shutdown, but only if ENVM = 0.

In direct-drive mode (HC_SEL = L) the regulator stops switching, the high-side PMOS disconnects the load from the input, and the LEDx pins are high impedance thus eliminating any DC conduction path. The TPS6132x device actively discharges the output capacitor when it turns off.

The integrated discharge resistor has a typical resistance of 2 kΩ, equally split between VOUT to BAL and BAL to GND outputs. The required time to discharge the output capacitor at VOUT depends on load current and the effective output capacitance. The active balancing circuit is disabled and the device consumes only a shutdown current of 1 μA (typical).

In high-current mode (HC_SEL = H), the device maintains its output biased at the input voltage level. The synchronous rectifier is current limited, for example, precharge current, in this mode, allowing external load, for example, an audio amplifier, to be powered with a restricted supply. The active balancing circuit is enabled and the device consumes only a standby current of 5 μA (typical).

9.4.10 Thermal Shutdown

As soon as the junction temperature, T_J, exceeds 160°C (typical), the device goes into thermal shutdown. In this mode, the power stage and the low-side current regulators are turned off, the HOTDIE bits are set and can only be reset by a readout.

In the voltage mode operation (MODE_CTRL = 11 or ENVM = 1), the device continues operation when the junction temperature falls below 140°C (typical) again. In the current regulation mode, DC-light or flashlight modes, the device operation is suspended.

9.5.1 TPS6132x I²C Update Sequence

The TPS6132x requires a start condition, a valid I²C address, a register address byte, and a data byte for a single update. After the receiving each byte, the TPS6132x device acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I²C address selects the TPS6132x. The TPS6132x performs an update on the falling edge of the acknowledge signal that follows the LSB byte.

Figure 49. Write Data Transfer Format in F/S-Mode

Figure 50. Read Data Transfer Format in F/S-Mode

Figure 51. Data Transfer Format in H/S-Mode

9.6.1 Slave Address Byte

The slave address byte is the first byte received following the START condition from the master device.

9.6.2 Register Address Byte

Following the successful acknowledgement of the slave address, the bus master sends a byte to the TPS6132x, which contains the address of the register to be accessed.

9.6.3 REGISTER0 (address = 0x00)

9.6.4 REGISTER1 (address = 0x01)

9.6.5 REGISTER2 (address = 0x02)

9.6.6 REGISTER3 (address = 0x03)

9.6.7 REGISTER4 (address = 0x04)

9.6.8 REGISTER5 (address = 0x05)

9.6.9 REGISTER6 (address = 0x06)

9.6.10 REGISTER7 (address = 0x07)