SLVSE48C january   2018  – may 2023 TPS65268-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Enable and Adjusting UVLO
      3. 7.3.3  Soft-Start Time
      4. 7.3.4  Power-Up Sequencing
      5. 7.3.5  V7V Low-Dropout Regulator and Bootstrap
      6. 7.3.6  Out-of-Phase Operation
      7. 7.3.7  Output Overvoltage Protection (OVP)
      8. 7.3.8  Slope Compensation
      9. 7.3.9  Overcurrent Protection
        1. 7.3.9.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.9.2 Low-Side MOSFET Overcurrent Protection
      10. 7.3.10 Power Good
        1. 7.3.10.1 Adjustable Switching Frequency
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Standby Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Loop Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The TPS65268-Q1 device is a monolithic triple synchronous step-down (buck) converter with 3-A, 2-A, 2-A output currents. The feedback voltage reference for each buck converter is 0.6 V. Each buck converter is independent with dedicated enable, soft-start, and loop compensation pins.

In the light load condition, the converter operates at continuous current mode (CCM) with a fixed frequency for optimized output ripple.

The TPS65268-Q1 device implements a constant-frequency, peak current-mode control that simplifies external loop compensation. The wide switching frequency of 200 kHz to 2.3 MHz allows for optimizing system efficiency, filtering size, and bandwidth. The switching frequency can be adjusted with an external resistor connecting between the ROSC pin and ground. The TPS65268-Q1 device also has an internal phase-locked loop (PLL) controlled by the ROSC pin that can be used to synchronize the switching cycle to the falling edge of an external system clock. The switching clock of BUCK1 is 180° out-of-phase operation from the clocks of BUCK2 and BUCK3 channels to reduce input current ripple, input capacitor size, and power-supply-induced noise.

The TPS65268-Q1 device is designed for safe monotonic startup into prebiased loads. The default startup is when the input voltage (VIN) is typically 3.8 V. The ENx pin can also be used to adjust the undervoltage lockout (UVLO) of the input voltage with an external resistor divider. In addition, the ENx pin has an internal 3.9-µA current source, so the ENx pin can be left floating to automatically power up the converters.

The TPS65268-Q1 device reduces the external component count by integrating the bootstrap circuit. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BST and LXx pins. A UVLO circuit monitors the bootstrap capacitor voltage (VBST-VLX) in each buck converter. When the VBST-VLX voltage drops to the threshold, the LXx pin is pulled low to recharge the bootstrap capacitor. The TPS65268-Q1 device can operate at 100% duty cycle as long as the bootstrap capacitor voltage is higher than the BOOT-LX UVLO threshold, which is typically 2.1 V.

The TPS65268-Q1 device has power-good comparators with hysteresis, which monitor the output voltages through internal feedback voltages. The device also features the PGOOD pin to supervise output voltages of the buck converter. When all buck converters are in the regulation range and power sequence is complete, the PGOOD pin is asserted high.

The soft-start and tracking pin (SSx) is used to minimize inrush currents or provide power-supply sequencing during power up. A small value capacitor or resistor divider is connected to the pin for soft-start or voltage tracking.

The TPS65268-Q1 device is protected from overload and overtemperature fault conditions. The converter minimizes excessive output overvoltage transients by taking advantage of the power-good comparator. During an output overvoltage condition, the high-side MOSFET is turned off until the internal feedback voltage is lower than 105% of the 0.6-V reference voltage. The TPS65268-Q1 device implements both high-side MOSFET overload protection and bidirectional low-side MOSFET overload protections to avoid inductor current runaway. If the overcurrent (OC) condition has lasted for more than the OC wait time (256 clock cycle), the converter shuts down and restarts after the hiccup time (8192 clock cycles). The TPS65268-Q1 device shuts down if the junction temperature is higher than thermal shutdown trip point. When the junction temperature drops 20°C typically below the thermal shutdown trip point, the TPS65268-Q1 device is restarted under control of the soft-start circuit automatically.