SLVSE48C january   2018  – may 2023 TPS65268-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Enable and Adjusting UVLO
      3. 7.3.3  Soft-Start Time
      4. 7.3.4  Power-Up Sequencing
      5. 7.3.5  V7V Low-Dropout Regulator and Bootstrap
      6. 7.3.6  Out-of-Phase Operation
      7. 7.3.7  Output Overvoltage Protection (OVP)
      8. 7.3.8  Slope Compensation
      9. 7.3.9  Overcurrent Protection
        1. 7.3.9.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.9.2 Low-Side MOSFET Overcurrent Protection
      10. 7.3.10 Power Good
        1. 7.3.10.1 Adjustable Switching Frequency
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Standby Operation
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Loop Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application Curves

GUID-D35FA52F-EFD6-425F-8C27-AAEC4E3CA0AA-low.png
IOUT = 3 A
Figure 8-3 BUCK1 Soft-Start
GUID-B5A4797A-565F-48DC-86E4-F5BA155DFC6A-low.png
IOUT = 2 A
Figure 8-5 BUCK3 Soft-Start
GUID-CFDD918B-0E5B-41FB-A1D9-7825C1A54112-low.png
IOUT = 2 A
Figure 8-7 BUCK2 Output Voltage Ripple
GUID-4EBB6508-1822-45FA-999F-EC7C9AF1972E-low.png
IOUT = 0.75 to 1.5 A SR = 0.25 A/µs
Figure 8-9 BUCK1 Load Transient
GUID-ADF85A89-736D-4E11-8191-C3159591A3D0-low.png
IOUT = 0.5 to 1 A SR = 0.25 A/µs
Figure 8-11 BUCK2 Load Transient
GUID-E43FC121-D970-4724-BD05-0745EA356DEE-low.png
IOUT = 0.5 to 1 A SR = 0.25 A/µs
Figure 8-13 BUCK3 Load Transient
GUID-20A7B4A8-418F-4225-B6D3-58967194F9D7-low.pngFigure 8-15 BUCK1 Hiccup and Recovery
GUID-375D54D8-DA5F-4ABB-85D0-1447AF95FCA3-low.pngFigure 8-17 BUCK3 Hiccup and Recovery
GUID-FEF48705-BDD4-4067-8BFE-BACC7A67C8AF-low.pngFigure 8-19 180° Out-of-Phase
GUID-81371B62-7548-42E7-962D-BB660282A1FA-low.gif
VIN = 5 V, VOUT1 = 1.5 V/2 A, VOUT2 = 1.2 V/1.5 A,
VOUT3 = 2.5 V/1.5 A,
TA = 25°C EVM condition 4 layers, 75 mm × 75 mm
Figure 8-21 Thermal Signature of TPS65268-Q1EVM Operating
GUID-6131B540-3E83-4384-9ABC-78B8457DE773-low.png
IOUT = 2 A
Figure 8-4 BUCK2 Soft-Start
GUID-514FBAD1-9085-40FC-B73D-CE10C1E6BC31-low.png
IOUT = 3 A
Figure 8-6 BUCK1 Output Voltage Ripple
GUID-695D04A0-0BD6-46D4-8CCA-5E51541112FA-low.png
IOUT = 2 A
Figure 8-8 BUCK3 Output Voltage Ripple
GUID-0E89719F-5756-4FC3-97C6-199087258732-low.png
IOUT = 1.5 to 2.25 A SR = 0.25 A/µs
Figure 8-10 BUCK1 Load Transient
GUID-E3373454-D34D-4EAC-B2FB-477588C2829C-low.png
IOUT = 1 to 1.5 A SR = 0.25 A/µs
Figure 8-12 BUCK2 Load Transient
GUID-1B3810E5-75F0-4C19-AB26-CC2F8F266AB7-low.png
IOUT = 1 to 1.5 A SR = 0.25 A/µs
Figure 8-14 BUCK3 Load Transient
GUID-1BDB6A71-6C3B-4419-8362-6061A42CC8AE-low.pngFigure 8-16 BUCK2 Hiccup and Recovery
GUID-5665FAE6-83C3-4CAD-A1CF-D45405E36654-low.pngFigure 8-18 PGOOD
GUID-8C81168E-ED0B-4622-8897-9D88E171E181-low.pngFigure 8-20 Synchronization With External Clock