SLVSAX7E August   2011  – August 2016 TPS65270

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjustable Switching Frequency
      2. 8.3.2  Out-of-Phase Operation
      3. 8.3.3  Delayed Start-Up
      4. 8.3.4  Soft-Start Time
      5. 8.3.5  Adjusting the Output Voltage
      6. 8.3.6  Error Amplifier
      7. 8.3.7  Slope Compensation
      8. 8.3.8  Overcurrent Protection
      9. 8.3.9  Thermal Shutdown
      10. 8.3.10 Low Power Mode Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With Minimum VIN (VIN < 4.45 V)
      2. 8.4.2 Operation With EN Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Bootstrap Capacitor Selection
        5. 9.2.2.5 Loop Compensation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Layout is a critical portion of PMIC designs.

  • Place VOUT, and LX on the top layer and an inner power plane for VIN.
  • Fit also on the top layer connections for the remaining pins of the PMIC and a large top side area filled with ground.
  • The top layer ground area sould be connected to the bottom ground layer(s) using vias at the input bypass capacitor, the output filter cpacitor and directly under the TPS65270 device to provide a thermal path from the Powerpad land to ground.
  • The AGND pin must be tied directly to the power pad under the IC and the power pad.
  • For operation at full rated load, the top side ground area together with the bottom ground plane, must provide adequate heat dissipating area.
  • There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin must be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the ground connections. Because the LX connection is the switching node, the output inductor must be placed close to the LX pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
  • The output filter capacitor ground must use the same power ground trace as the VIN input bypass capacitor. Try to minimize this conductor length while maintaining adequate width.
  • The compensation must be as close as possible to the COMP pins. The COMP and OSC pins are sensitive to noise so the components associated to these pins must be placed as close as possible to the IC and routed with minimal lengths of trace.

11.2 Layout Example

TPS65270 layout_slvsax7.gif Figure 18. Example Layout for the TPS65270

11.3 Power Dissipation

The total power dissipation inside TPS65270 must not exceed the maximum allowable junction temperature of 125°C to maintain reliable operation. The maximum allowable power dissipation is a function of the thermal resistance of the package (RθJA) and ambient temperature.

To calculate the temperature inside the device under continuous loading use the following procedure.

  1. Define the set voltage for each converter.
  2. Define the continuous loading on each converter. Make sure do not exceed the converter maximum loading.
  3. Determine from the graphs below the expected losses in watts per converter inside the device. The losses depend on the input supply, the selected switching frequency, the output voltage and the converter chosen.
  4. To calculate the maximum temperature inside the IC use the following formula:
    5. Equation 14. TPS65270 eq9_hotspot_lvsaa3.gif

    where

    • PDIS is the sum of losses in all converters
    • RθJA is the junction to ambient thermal impedance of the device and it is heavily dependant on board layout
TPS65270 pwr_diss1_lvsax7.gif
VIN = 12 V fSW = 500 kHz
VOUT (from top to bottom) = 5 V, 3.3 V, 2.5 V, 1.8 V, 1.2 V
Figure 19. Buck 1
TPS65270 pwr_diss3_lvsax7.gif
VIN = 12 V fSW = 500 kHz
VOUT (from top to bottom) = 5 V, 3.3 V, 2.5 V, 1.8 V, 1.2 V
Figure 21. Buck 2
TPS65270 pwr_diss2_lvsax7.gif
VIN = 12 V fSW = 1.1 MHz
VOUT (from top to bottom) = 5 V, 3.3 V, 2.5 V, 1.8 V, 1.2 V
Figure 20. Buck 1
TPS65270 pwr_diss4_lvsax7.gif
VIN = 12 V fSW = 1.1 MHz
VOUT (from top to bottom) = 5 V, 3.3 V, 2.5 V, 1.8 V, 1.2 V
Figure 22. Buck 2