SBVS047I April   2004  – November 2023 TPS715A

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Wide Supply Range
      2. 6.3.2 Low Supply Current
      3. 6.3.3 Current Limit
      4. 6.3.4 Dropout Voltage (VDO)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting VOUT for the TPS715A01 Adjustable LDO
        2. 7.2.2.2 External Capacitor Requirements
        3. 7.2.2.3 Input and Output Capacitor Requirements
        4. 7.2.2.4 Reverse Current
        5. 7.2.2.5 Feed-Forward Capacitor (CFF)
        6. 7.2.2.6 Power Dissipation (PD)
        7. 7.2.2.7 Estimating Junction Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Power Dissipation
      2. 7.5.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Module
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRV|6
  • DRB|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted)

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Figure 5-1 TPS715A33 Output Voltage vs Output Current (Legacy Chip)
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Figure 5-3 TPS715A33 Output Voltage vs Input Voltage
(New Chip)
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Figure 5-5 Output Voltage vs Junction Temperature (New Chip)
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Figure 5-7 Ground Current vs Junction Temperature
(New Chip)
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Figure 5-9 Ground Pin Current vs Load Current (New Chip)
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Figure 5-11 TPS715A33 Dropout Voltage vs Output Current (New Chip)
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Figure 5-13 TPS715A01 Dropout Voltage vs Input Voltage
(New Chip)
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Figure 5-15 TPS715A33 Dropout Voltage vs Junction Temperature (New Chip)
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Figure 5-17 Output Spectral Noise Density vs Frequency
(New Chip)
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Figure 5-19 Output Voltage vs Current Limit (Legacy Chip)
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Figure 5-21 Current Limit vs Junction Temperature (New Chip)
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Figure 5-23 Power-Supply Ripple Rejection vs Frequency
(New Chip)
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Figure 5-25 Power-Up, Power-Down (New Chip)
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Figure 5-27 Fast Power-Up (New Chip)
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Figure 5-29 Line Transient Response (New Chip)
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Figure 5-31 Load Transient Response (New Chip)
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Figure 5-33 Dropout Exit Transient Response (New Chip)
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Figure 5-2 TPS715A33 Output Voltage vs Output Current
(New Chip)
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Figure 5-4 Output Voltage vs Junction Temperature
(Legacy Chip)
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Figure 5-6 Ground Current vs Junction Temperature
(Legacy Chip)
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Figure 5-8 Ground Pin Current vs Input Voltage (New Chip)
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Figure 5-10 TPS715A33 Dropout Voltage vs Output Current (Legacy Chip)
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Figure 5-12 TPS715A01 Dropout Voltage vs Input Voltage (Legacy Chip)
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Figure 5-14 TPS715A33 Dropout Voltage vs Junction Temperature (Legacy Chip)
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Figure 5-16 Output Spectral Noise Density vs Frequency (Legacy Chip)
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Figure 5-18 Output Impedance vs Frequency (Legacy Chip)
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Figure 5-20 Output Voltage vs Current Limit (New Chip)
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Figure 5-22 Power-Supply Ripple Rejection vs Frequency (Legacy Chip)
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Figure 5-24 Power-Up and Power-Down (Legacy Chip)
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Figure 5-26 Fast Power-Up (Legacy Chip)
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Figure 5-28 Line Transient Response (Legacy Chip)
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Figure 5-30 Load Transient Response (Legacy Chip)
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Figure 5-32 Line Transient Response (New Chip)