SLUSBA5F December   2012  – March 2018 UCC27611

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD and Undervoltage Lockout
      2. 7.3.2 Operating Supply Current
      3. 7.3.3 Input Stage
      4. 7.3.4 Enable Function
      5. 7.3.5 Output Stage
      6. 7.3.6 Low Propagation Delays
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Drive Supply Voltage
        2. 8.2.2.2 Input Configuration
        3. 8.2.2.3 Output Configuration
        4. 8.2.2.4 Power Dissipation
        5. 8.2.2.5 Thermal Considerations
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Input Stage

The input pins of the UCC27611 device is based on a TTL and CMOS compatible input threshold logic that is independent of the VDD supply voltage. With typical high threshold = 2.05 V and typical low threshold = 1.1 V, the logic level thresholds can be conveniently driven with PWM control signals derived from 3.3-V and 5-V digital power controllers. Wider hysteresis (typical 1 V) offers enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V. These devices also feature tight control of the input pin threshold voltage levels, which eases system design considerations, and ensures stable operation across temperature. The very low input capacitance on these pins reduces loading, and increases switching speed.

The device features an important safety function wherein, whenever any of the input pins are in a floating condition, the output of the respective channel is held in the low state. This is achieved using VDD pullup resistors on all the inverting inputs (IN– pin), or GND pulldown resistors on all the noninverting input pins (IN+ pin)(see Functional Block Diagram).

The device also features a dual input configuration, with two input pins available to control the state of the output. The user has the flexibility to drive the device using either a noninverting input pin (IN+), or an inverting input pin (IN–). The state of the output pin is dependent on the bias of both the IN+ and IN– pins. See Table 1 input and output logic truth table, and the Figure 12 for additional clarification.