With ordinary flyback converters, the output capacitance value is typically determined by the transient response requirement for a specific load step, I_TRAN, sometimes from a no-load condition. For example, in some USB charger applications, there is requirement to maintain a transient minimum V_O of 4.1 V with a load-step of 0 mA to 500 mA. Equation 20 below assumes that the switching frequency can be at the UCC28730-Q1 minimum of f_SW(min).

Equation 20.

This results in a C_OUT value of over 17,000 µF, unless a substantial pre-load is used to raise the minimum switching frequency. However, the wake-up feature allows the use of a much smaller value for C_OUT because the wake-up response immediately cancels the Wait state and provides high-frequency power cycles to recover the output voltage from the load transient. The secondary-side voltage monitor UCC24650 provides the UCC28730-Q1 with a wake-up signal when it detects a -3% droop in output voltage.

Equation 21.

where

• (dV_OUT/dt) is the slope at which the UCC24650 must detect the V_OUT droop. Use a slope factor of 3700 V/s or lower for this calculation.

The UCC28730-Q1 incorporates internal voltage-loop compensation circuits so that external compensation is not necessary, provided that the value of C_OUT is high enough. The following equation determines a minimum value of C_OUT necessary to maintain a phase margin of about 40 degrees over the full-load range. K_Co is a dimensionless factor which has a value of 100.

Equation 22.

Another consideration for selecting the output capacitor(s) is the maximum ripple voltage requirement, V_RIPPLE(max), which is reviewed based on the maximum output load, the secondary-peak current, and the equivalent series resistance (ESR) of the capacitor. The two major contributors to the output ripple voltage are the change in V_OUT due to the charge and discharge of C_OUT between each switching cycle and the step in V_OUT due to the ESR of C_OUT. TI recommends an initial allocation of 33% of V_RIPPLE(max) to ESR, 33% to C_OUT, and the remaining 33% to account for additional low-level ripple from EMI-dithering, valley-hopping, sampling noise and other random contributors. In Equation 23, a margin of 50% is applied to the capacitor ESR requirement to allow for aging. In Equation 24, set ΔV_CQ = 0.33 x V_RIPPLE(max) to determine the minimum value of C_OUT with regard to ripple voltage limitation. If other allocations of the allowable ripple voltage are desired, these equations may be adjusted accordingly.

Equation 23.

Equation 24.

Choose the largest value of the previous C_OUT calculations for the minimum output capacitance. If the value of C_OUT becomes excessive to meet a stringent ripple limitation, a C-L-C pi-filter arrangement can be considered to as an alternative to a simple capacitor-only filter. This arrangement is beyond the scope of this datasheet.