8.6.16 ALERT_PIN_CFG Register (Address = 0x17) [reset = 0x0]
ALERT_PIN_CFG is shown in Figure 52 and described in Table 30.
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Figure 52. ALERT_PIN_CFG Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
ALERT_DRIVE |
ALERT_LOGIC[1:0] |
R-0b |
R/W-0b |
R/W-0b |
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Table 30. ALERT_PIN_CFG Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-3 |
RESERVED |
R |
0b |
Reserved. Reads return 0. |
2 |
ALERT_DRIVE |
R/W |
0b |
Configure output drive of the ALERT pin.
0b = Open-drain output. Connect external pullup resistor.
1b = Push-pull output.
|
1-0 |
ALERT_LOGIC[1:0] |
R/W |
0b |
Configure how ALERT pin is asserted.
0b = Active low.
1b = Active high.
10b = Pulsed low (one logic low pulse one time per alert flag).
11b = Pulsed high (one logic high pulse one time per alert flag).
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