JAJSDX6A september   2017  – july 2023 ADS8588H

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: CONVST Control
    7. 6.7  Timing Requirements: Data Read Operation
    8. 6.8  Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together
    9. 6.9  Timing Requirements: Parallel Data Read Operation, CS and RD Separate
    10. 6.10 Timing Requirements: Serial Data Read Operation
    11. 6.11 Timing Requirements: Byte Mode Data Read Operation
    12. 6.12 Timing Requirements: Oversampling Mode
    13. 6.13 Timing Requirements: Exit Standby Mode
    14. 6.14 Timing Requirements: Exit Shutdown Mode
    15. 6.15 Switching Characteristics: CONVST Control
    16. 6.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together
    17. 6.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separate
    18. 6.18 Switching Characteristics: Serial Data Read Operation
    19. 6.19 Switching Characteristics: Byte Mode Data Read Operation
    20. 6.20 Timing Diagrams
    21. 6.21 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Clamp Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Third-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Digital Filter and Noise
      8. 7.3.8  Reference
        1. 7.3.8.1 Internal Reference
        2. 7.3.8.2 External Reference
        3. 7.3.8.3 Supplying One VREF to Multiple Devices
      9. 7.3.9  ADC Transfer Function
      10. 7.3.10 ADS8588H Device Family Comparison
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface: Pin Description
        1. 7.4.1.1  REFSEL (Input)
        2. 7.4.1.2  RANGE (Input)
        3. 7.4.1.3  STBY (Input)
        4. 7.4.1.4  PAR/SER/BYTE SEL (Input)
        5. 7.4.1.5  CONVSTA, CONVSTB (Input)
        6. 7.4.1.6  RESET (Input)
        7. 7.4.1.7  RD/SCLK (Input)
        8. 7.4.1.8  CS (Input)
        9. 7.4.1.9  OS[2:0]
        10. 7.4.1.10 BUSY (Output)
        11. 7.4.1.11 FRSTDATA (Output)
        12. 7.4.1.12 DB15/BYTE SEL
        13. 7.4.1.13 DB14/HBEN
        14. 7.4.1.14 DB[13:9]
        15. 7.4.1.15 DB8/DOUTB
        16. 7.4.1.16 DB7/DOUTA
        17. 7.4.1.17 DB[6:0]
      2. 7.4.2 Device Modes of Operation
        1. 7.4.2.1 Power-Down Modes
          1. 7.4.2.1.1 Standby Mode
          2. 7.4.2.1.2 Shutdown Mode
        2. 7.4.2.2 Conversion Control
          1. 7.4.2.2.1 Simultaneous Sampling on All Input Channels
          2. 7.4.2.2.2 Simultaneous Sampling Two Sets of Input Channels
        3. 7.4.2.3 Data Read Operation
          1. 7.4.2.3.1 Parallel Data Read
          2. 7.4.2.3.2 Parallel Byte Data Read
          3. 7.4.2.3.3 Serial Data Read
          4. 7.4.2.3.4 Data Read During Conversion
        4. 7.4.2.4 Oversampling Mode of Operation
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報
Serial Data Read

The ADS8588H also supports a serial interface mode for reading the device output data. This interface mode is selected by applying a logic high input on the PAR/SER/BYTE SEL input pin and a logic low input on the DB15/BYTE SEL input pin. This interface mode uses a CS control input, a communication clock input (SCLK), BUSY and FRSTDATA output indicators, and serial data output lines DOUTA and DOUTB.

Figure 6-5 illustrates the timing diagram for data read in serial mode for one channel of the ADC, framed by the CS signal. When the CS input is high, the serial data output and FRSTDATA output lines are in tri-state and the SCLK input is ignored. On the falling edge of the CS signal, the output lines become active and the MSB of the conversion result comes out on DOUTA, DOUTB. The MSB can be read by the host processor on the next falling edge of the SCLK signal. The remaining 15 bits of the conversion result are output on the subsequent rising edges of the SCLK signal and can be read by the host processor on the corresponding falling edges. Thus, a total of 16 SCLK cycles are required to clock out 16 bits of conversion result for each channel and the same process can be repeated for the remaining channels in an ascending order. The CS input can be left at a logic low level for the entire data retrieval process for all analog channels or used to frame the retrieval of the 16-bit output data for each analog channel.

The ADS8588H can output the conversion on one or both of the serial data output lines, DOUTA and DOUTB. The conversion results from the first set of channels (channels 1-4) appear first on DOUTA, followed by the second set of channels (channels 5-8) if only DOUTA is used for reading data. This order is reversed for DOUTB, in which the second set of channels appear first followed by the first set of channels. The use of both data output lines reduces the time needed for data retrieval and a higher throughput can therefore be achieved in this mode.

The FRSTDATA output is in tri-state when the CS signal is high. As illustrated in Figure 6-5, FRSTDATA goes high on the first falling edge of the CS signal when the MSB of channel 1 is output on DOUTA. The FRSTDATA output remains high for the next 16 SCLK cycles until all data bits of channel 1 are read from the device. The FRSTDATA output returns to a logic low level at the 16th falling edge of the SCLK signal. If data are also read on DOUTB in serial mode, then FRSTDATA remains high when the first channel of the second set of channels is read from the device. The high state of FRSTDATA corresponds to channel 5.

Based on the above description of the different pins in the serial interface mode, conversion data can be read out of the device in several different ways. Some example recommendations are provided below:

  • The conversion data can be read out of the device using only one of the two serial output lines, DOUTA or DOUTB. In this case, using DOUTA for output data read back is recommended because channel 1 data appear first on DOUTA followed by the data for other channels in ascending order. To read the data for all channels, provide a total of 16 × 8 = 128 SCLK cycles. This entire data frame can be created within a single CS pulse or each group of 16 SCLK cycles can be individually framed by the CS signal. The primary disadvantage of using just one data line for reading conversion data is that the throughput is reduced if a data read operation is performed after conversion. Figure 7-18 illustrates this operation.
  • Alternatively, only DOUTB can be used for reading the conversion data from all channels. In this case, everything else remains the same and the output bit stream contains data for all channels in the following order: channels 5, 6, 7, 8, 1, 2, 3, and 4. Figure 7-18 illustrates this operation.
    GUID-ACD4F66E-367E-46DB-A01A-9B0FEDE632BB-low.gifFigure 7-18 Data Read Back in the Serial Interface Using Either DOUTA or DOUTB Timing Diagram
  • In order to minimize the time for the data read operation in serial mode, both DOUTA and DOUTB can be used to read data out of the device. In this case, the conversion results from the first set of channels (channels 1-4) appear on DOUTA and the conversion results from the second set of channels (channels 5-8) appear first on DOUTB. To read the data for all channels, provide a total of 16 × 4 = 64 SCLK cycles. This entire data frame can be created within a single CS pulse or each group of 16 SCLK cycles can be individually framed by the CS signal. Figure 7-19 shows an example timing diagram.
    GUID-99B39FA8-F88A-4D01-8956-534733032D2D-low.gifFigure 7-19 Data Read Back in the Serial Interface Using Both DOUTA and DOUTB Timing Diagram