The AFEx8201 feature a register built-in self-test (RBIST) that runs on all the registers listed in Table 7-11 through a CRC calculation in the order the registers are listed in Table 7-11. If the final CRC value is zero, then no error is present in the configuration of the registers. If a non-zero value is present at the end of the calculation, then there is a configuration error. The polynomial used has a Hamming distance (HD) of 4 for data packets up to 2048 bits. With HD = 4, the CRC detects any combination of 4-bit errors within the stored data. Independently calculate the expected CRC polynomial and store the output in the RBIST_CRC register at 3Fh.

The final value of the CRC is read in the CRC_RD register at address 3Eh. This value is updated while either an RBIST or shadow load is running. Both the RBIST and OTP memory use the same CRC calculation engine and polynomial. The value in the CRC_RD register remains constant until another RBIST or SHADOWLOAD in TRIGGER register (0Ah) is triggered.

Set TRIGGER.RBIST to 1 to initiate an RBIST. The TRIGGER.RBIST bit stays high as long as the RBIST is running and clears when the self-test is complete. While the RBIST is running, the registers cannot be written to or read. Send NOP commands and monitor the RBIST SDO status bit to determine if the RBIST has completed.

Set the GEN_STATUS.RBIST_MODE bit to 1 to enable the RBIST. This bit is sticky until the GEN_STATUS register is read.

The 16-bit CRC used to generate the RBIST is the openSAFETY (0x755B) with the following polynomial:

x¹⁶ + x¹⁴ + x¹³ + x¹² + x¹⁰ + x⁸ + x⁶ + x⁴ + x³ + x¹ + 1.

The list of registers covered by the RBIST is listed in Table 7-11. Not all registers feature the RBIST.